MIPI RFFE Synthesizable Transactor provides a smart way to verify the MIPI RFFE component of a SOC or a ASIC in Emulator or FPGA platform. MIPI RFFE Synthesizable Transactor provides an smart way to verify the MIPI RFFE bi-directional two-wire bus. The SmartDV's MIPI RFFE Synthesizable Transactor is fully compliant with version 1.0,2.0 and 2.1 MIPI Alliance specification for RF Front-End Control Interface and provides the following features.
MIPI RFFE Synthesizable Transactor
Overview
Key Features
- Supports 1.0,2.0 and 2.1 MIPI RFFE Specifications
- Supports Full MIPI RFFE Master and Slave functionality
- Operates as a Master, Slave, or both
- Supports all topologies as per the MIPI RFFE specification
- Supports multiple slaves
- Supports following frames
- Command Frame
- Data/Address Frame
- No Response Frame
- Bus ownership transfer
- Interrupt polling
- Master write and read
- Master context write and context read
- Supports various kind of Master and Slave errors generation
- Undefined command frame
- Command frame with parity error
- Command frame length error
- Address frame with parity error
- Data frame with parity error
- Read of unused register
- Write of an unused register
- Read using the broadcast ID or a GSID
- Various errors in Bus ownership transfer
- Supports glitch monitor and injection
- Support injection of glitch at all positions of SDATA
- Support injection of glitch at all positions of SCLK
- Supports detection of glitches
- Supports extended register read/writes
- Supports interrupt summary and identification command sequence
- Supports Master ownership handover
- Support Master write and read sequence
- Supports device enumeration
- Supports low power testing
- Supports bus-accurate timing
- Supports half speed
- Status counters for various events in bus
- Notifies the testbench of significant events such as transactions, warnings, timing and protocol violations
- MIPI RFFE Synthesizable Transactor comes with complete testsuite to test every feature of MIPI RFFE specification
Benefits
- Compatible with testbench writing using SmartDV's VIP
- All UVM sequences/testcases written with VIP can be reused
- Runs in every major emulators environment
- Runs in custom FPGA platforms
Block Diagram
Deliverables
- Synthesizable transactors
- Complete regression suite containing all the MIPI RFFE testcases
- Examples showing how to connect various components, and usage of Synthesiable VIP
- Detailed documentation of all DPI, class, task and functions used in verification env
- Documentation contains User's Guide and Release notes