The MIPI RFFE Slave controller IP is a highly optimized and technology and PHY agnostic implementation of the MIPI RFFE v.3.1 standard targeting both ASIC and FPGA technologies. This IP is used to connect a digital RFIC to RF front end components, like Power Amplifiers (PA), Low-Noise Amplifiers (LNA), filters, switches, power management modules, Antenna Turner and Sensors,which are considered RFFE Slaves. This MIPI RFFE Slave IP is backward compatible with MIPI RFFE components version 3.0, 2.1, 2.0 and 1.0.
The IP-core has been rigorously tested in System Verilog random regression environment.
The MIPI RFFE Slave IP core is a highly optimized Silicon Agnostic implementation of the MIPI RFFE protocol version 3.1, used to connect a digital RFIC to RF Front end components, targeting both ASIC and FPGA’s. It delivers all features of the standard and allows for great configurability of features.
The IP support a configurable amount of slave device registers in 3 separate groups. Making it possible to build the most complex of systems.
Trigger remapping, and timed trigger operation, allow to make efficient use of the slave registers via the shadow register mechanism, coordinating the register value changes to specific points in time.
Trigger remapping, and timed trigger operation, allow to make efficient use of the slave registers via the shadow register mechanism, coordinating the register value changes to specific points in time.
