IP Catalog > Interface IP > Interconnect IP > MIPI IP > MIPI PHY IP > MIPI M-PHY IP > MIPI M-PHY G4 Type 1 2Tx2RX in TSMC (16nm, 12nm, N7, N6, N5, N4, N3E)

MIPI M-PHY G4 Type 1 2Tx2RX in TSMC (16nm, 12nm, N7, N6, N5, N4, N3E)

Overview

The silicon-proven Synopsys MIPI® M-PHY IP, compliant with the latest MIPI
M-PHY v5.0 specification, supports speeds up to 23.32 Gbps per lane. The IP is optimized for a broad range of high-speed interfaces for applications including JEDEC Universal Flash Storage (UFS) and UniPro interfaces which are widely used in mobile and automotive applications.
The Synopsys M-PHY IP, ideal for embedded storage and chip-to-chip communication, provides low-power features, fast transitions between high- speed burst to low power saving modes, and the ability to manage the TX and RX directions independently.
The Synopsys MIPI M-PHY IP supports HS Gear1, Gear2, Gear3, Gear4 and Gear5 rates ranging from 1.248 Gbps to 23.32 Gbps per lane. Low-speed capabilities are available with Gear1 to Gear5 PWM modes. A sophisticated clock recovery mechanism and power-efficient clock circuitry are designed to guarantee the integrity of the clocks and signals needed to meet strict timing requirements. The Synopsys MIPI M-PHY IP supports large and small amplitudes, slew rate control and dithering functionality for optimized electromagnetic interference (EMI).
The Synopsys MIPI M-PHY IP along with Synopsys Universal Flash Storage (UFS) Host Controller IP or Synopsys MIPI UniPro Controller IP provides a single vendor UFS IP solution that designers can easily integrate into application processors with less risk, while speeding time-to-market of advanced SoCs and device integrated circuits (ICs).

Key Features

  • Compliant with either the MIPI M-PHY v5.0 or MIPI M-PHY v4.1 specification as M-PHY Type-I
  • Supports MIPI UniPro, JEDEC UFS protocols
  • Supports High-Speed (HS) Gear1, Gear2, Gear3, Gear4 and Gear5 4 A/B modes
  • Low-speed Pulse-Width Modulation (PWM) Gear1 to Gear5 in Type-I LS implementation
  • Extended reference clock support: 19.2, 26, 38.4 and 52MHz
  • Optimized lower power and hibernation mode to minimize energy consumption
  • Fast entering and recovery from/to low-power modes
  • Optimized EMI performance through the use of slew rate control and dithering
  • Large and small amplitude
  • Sophisticated clock recovery mechanism
  • Power efficient clock circuitry for high-speed and low-speed clock generation
  • Supports advanced process technologies
  • Easily integrates with Synopsys MIPI UniPro and UFS Host Controller IP

Benefits

  • Compliant with MIPI M-PHY v5.0 specification
  • Supports MIPI UniPro, JEDEC UFS protocols
  • Supports High-Speed (HS) Gear1, Gear2, Gear3, Gear4 and Gear5 A/B modes
  • Supports M-PHY Type-I
  • Modular architecture allows multiple lane configurations
  • Low-speed Pulse-Width Modulation (PWM) Gear1 to Gear5 in Type-I LS implementation
  • Low-power operation, small area and low latency
  • Supports advanced process technologies
  • Easily integrates with Synopsys MIPI UniPro and UFS Host

Applications

  • Smartphones
  • Tablets, ultrabooks,
  • Automotive ADAS and infotainment
  • Chip-to-chip low-power interconnects
  • Flash Storage Devices
  • Gaming
  • Digital cameras, camcorders
  • Hard Disk Drives (HDD)
  • Wireless communication
  • Set-top boxes
  • Smart TVs
  • Drones
  • Augmented/virtual reality

Deliverables

  • Databook
  • Application notes
  • Integration guidelines
  • Verilog behavioral model
  • Abstract LEF and timing LIB files
  • GDSII layout database

Technical Specifications

Foundry, Node
TSMC 16nm, 12nm, N7, N6, N5, N4, N3E - FFC, FF, EFF
Availability
Contact the Vendor
TSMC
Pre-Silicon: 3nm , 4nm , 5nm , 6nm , 7nm , 12nm , 16nm
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