IP Catalog > Interface IP > Interconnect IP > MIPI IP > MIPI Controller IP > MIPI I3C IP > MIPI I3C Verification IP

MIPI I3C Verification IP

Overview

MIPI I3C Verification IP provides a smart way to verify the MIPI I3C bi-directional two-wire bus. The SmartDV's MIPI I3C Verification IP is fully compliant with MIPI I3C version 1.0, Draft version 1.1 and HCI version 1.0, Draft version 1.1 and 2.0 specifications.

MIPI I3C Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

MIPI I3C Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key Features

  • Compliant with MIPI I3C version 1.1 specification.
  • Full MIPI I3C Master and Slave functionality
  • Two wire serial interface up to 12.5 MHz
  • Supports all MIPI I3C Device Types.
  • Supports all topologies.
    • Multi Master-Multi Slave
    • Multi Master-Single Slave
    • Single Master-Multi Slave
    • Single Master-Single Slave
  • Legacy I2C Device co-existence on the same Bus
  • Supports Dynamic Address Assignment including Static Addressing for legacy I2C Devices.
  • Supports I3C Address Arbitration.
  • Supports Single Data Rate (SDR) Messaging.
    • I3C Coding SDR
    • I3C Coding SDR with CCC Directed addressing
    • I3C Coding SDR with CCC Broadcasted addressing
  • Supports High Data Rate (HDR) Messaging.
    • HDR-Dual Data Rate Mode (HDR-DDR)
    • HDR-Ternary Symbol Legacy Mode (HDR-TSL)
    • HDR-Ternary Symbol Pure-Bus Mode (HDR-TSP)
    • HDR Bulk Transport Mode (HDR-BT)
  • Support Multi-Lane(ML) Data transfer.
  • SDR Based ML Frame Formats
    • SDR-ML DUAL & QUAD Coding
  • HDR-DDR Based ML Frame Formats
    • DDR-ML DUAL & QUAD Coding
  • HDR-TSP Based ML Frame Formats
    • TSP-ML DUAL & QUAD Coding
  • HDR-BT Based ML Frame Formats
    • BT-ML DUAL & QUAD Coding
  • Support for Device to Device(s) Tunneling.
  • In-Band Interrupt support
  • Hot-Join request support
  • Secondary Master Request Support
  • Support for all I3C Common Command Codes (CCCs).
    • Supports CCC framing in HDR-DDR/TSL/TSP/BT modes.
    • Supports HDR-DDR ML Coding and interoperability for CCC’s.
  • Supports mixing of various Message types.
  • 7 bit configurable Slave address
  • Supports I2C 50 ns glitch filter for I2C Devices.
  • Supports I2C START byte generation and handling.
  • Bus-accurate timing
  • Glitch insertion and detection
  • Supports Master/Slave arbitration and clock synchronization.
  • Supports insertion of wait states by Slave and Master.
  • Slave supports control of response fields including NACK, Data and Slave busy.
  • Supports Error Handling
  • Supports Slave Reset and Bus Recovery.
  • Supports slave error types S0-S6, SM0.
  • Supports master error types M0-M3.
  • Supports injection of various errors.
    • Master aborting in middle of access
    • Master doing ACK on last read access
    • Master continue after NACK from Slave for write data
    • Glitch injection on clock and data at various windows
    • Random and Periodic clock period stretching by Slave
    • Random Write NACK insertion by Slave
    • CRC and Parity error
  • Callbacks in Master, Slave and Monitor for user processing of data.
  • Notifies the testbench of significant events such as transactions, warnings, timing and protocol violations.
  • Functional coverage of complete MIPI I3C specs.
  • MIPI I3C Verification IP comes with complete testsuite to test every feature of MIPI I3C specification.
  • Specific features of HCI Verification
  • Compliant with HCI version 1.0 and Draft version 1.1 and 2.0 specification
  • Supports predictive addressing scheme.
  • Supports Direct commands.
  • DMA interface support (DMA Mode)
    • Single transfer descriptor defines Command and Data
    • Single response status descriptor reports status of the transfer
    • Linked descriptor support (Multicast messaging support)
  • PIO Interface support (PIO Mode)
    • Command Queue Operation
    • Response Queue Operation
    • IBI Queue Operation
  • Auto-Reject for In-Band Interrupt and Hot-Join (NACK and directed DISEC CCC to
  • disable)
  • Supports below Descriptors,
    • Address Assignment Command
    • Legacy transfer Descriptors
    • Immediate data transfer
    • Regular data transfer
    • Unified Data Transfer Command
    • Extra Immediate Data Transfer Command
    • Internal Control Command
    • Response Descriptor
    • IBI Status Descriptor
    • Secondary master command, request and response Descriptor
    • Combo transfer Descriptor
  • Supports DCT and DAT tables
  • Supports Data Byte Ordering
  • Supports below features,
    • Scatter-Gather
    • Time-stamping
    • Auto-Command
    • Scheduled Commands
    • Global Commands
  • DMA Mode with Command Rings to enable clean Doorbell mechanisms
    • Multiple Command/Response Rings and IBI Rings, including IBI payload
    • Supports for interrupt masking.

    Benefits

    • Faster testbench development and more complete verification of MIPI I3C designs.
    • Easy to use command interface simplifies testbench control and configuration of TX and RX.
    • Simplifies results analysis.
    • Runs in every major simulation environment.

    Block Diagram

    MIPI I3C Verification IP Block Diagram

    Deliverables

    • Complete regression suite containing all the MIPI I3C testcases to certify MIPI I3C Slave/Master device
    • Examples showing how to connect various components and usage of Master, Slave and Monitor.
    • Detailed documentation of all class, task and function's used in verification env.
    • Documentation also contains User's Guide and Release notes.

    Technical Specifications

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