MIPI I3C PSVIP

Overview

MIPI I3C Post Silicon Validation IP (MIPI I3C Protocol Analyzer And Exerciser) provides a smart way to post silicon validation of the MIPI I3C component of a SOC. MIPI I3C Post Silicon Validation IP provides an smart way to post silicon validation of the MIPI I3C bi-directional two-wire bus.The SmartDV's MIPI I3C Post Silicon Validation IP is fully compliant with Specification for I3C version 1.1 of the MIPI I3C Bus Specification and provides the following features.

MIPI I3C PSVIP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

MIPI I3C PSVIP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key Features

Compliant with MIPI I3C version 1.1 specification
Supports full MIPI I3C Master and Slave functionality
Two wire serial interface up to 12.5 MHz using Push-Pull with the following Data rates supported

Standard speed

Supports all topologies

Single master – Single slave
Single master – Multi slave
Multi master – Single slave
Multi master – Multi slave

Dynamic Addressing while supporting Static Addressing for legacy I2C devices.
Supports I3C address arbitration.
Supports Single Data Rate (SDR) messaging.

Direct CCC
Broadcast CCC

Supports High Data Rate (HDR) messaging

HDR-Dual Data Rate Mode (HDR-DDR)
HDR-Ternary symbol for Pure bus (HDR-TSP)
HDR-Ternary symbol Legacy inclusive bus (HDR-TSL)

In-Band Interrupt support and Hot-Join support
Legacy I2C Device co-existence on the same Bus instance
Supports error detection and recovery
Supports injection of various errors by master

Broadcast address/ I3C address error
SDR write data parity error
Dynamic address parity error
Illegal CCC error
HDR command parity and preamble error
HDR write data parity and preamble error
HDR CRC and frame error

Supports injection of various errors by slave

Broadcast address/ I3C address nack error
Illegal CCC error
I2C write data nack error
SDR read data parity error
HDR read data preamble and parity error
HDR read CRC error

Benefits

Runs in custom FPGA platforms
Validate I3C device for compliance

Block Diagram

Deliverables

Linux Perl Driver to control the PSVIP
Encrypted RTL of PSVIP or Bit file for selected FPGA platform
Complete regression suite containing all the MIPI I3C testcases
Detailed documentation of all functions of perl driver and testcases
Documentation also contains User's Guide and Release notes

Technical Specifications

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