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MIPI HTI Verification IP

Overview

MIPI HTI Verification IP Provides to debug the information in microcontroller,microprocessor over high speed serial transmission. The SmartDV's MIPI HTI Verification IP is fully compliant with version 1.0 and 1.1 MIPI Alliance specification and verifies MIPI HTI Interfaces.

MIPI HTI Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

MIPI HTI Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key Features

  • Supports MIPI HTI version 1.0 and 1.1 specification.
  • Supports Point-to-point topology
  • Supports multiple lanes up to 8 lanes.
  • Supports NRZ line encoding.
  • Supports full of unidirectional duplex from TX to RX.
  • Supports aurora 8b/10b Encode and Decode functions
  • Supports test pattern LFSR.
  • Supports user flow control (UFC).
  • Supports following bit rates
    • 1.62 Gbps
    • 1.65 Gbps
    • 2.5 Gbps
    • 2.7 Gbps
    • 3 Gbps
    • 3.125 Gbps
    • 3.4 Gbps
    • 4.2 Gbps
    • 5 Gbps
    • 5.4 Gbps
    • 6 Gbps
    • 6.25 Gbps
    • 8 Gbps
    • 8.1 Gbps
    • 8.5 Gbps
    • 10 Gbps
    • 10.3125 Gbps
    • 12 Gbps
    • 12.5 Gbps
    • 16 Gbps
  • Support following 8b/10b error insertion and detection,
    • Invalid K character injection
    • Injection of disparity errors
    • Wrong K character injection
  • Full MIPI HTI Transmitter and Receiver functionality.
  • Supports clock recovery.
  • Supports constraints randomization.
  • Supports monitor, detects and notifies the test bench of all protocol and timing errors.
  • Supports status counters for various events in bus.
  • Supports callbacks in node transmitter, receiver and monitor for user processing of data.
  • MIPI HTI Verification IP comes with complete test suite to test every feature of MIPI HTI specification.
  • Supports functional coverage for complete MIPI HTI features.

Benefits

  • Faster testbench development and more complete verification of MIPI HTI designs.
  • Easy to use command interface simplifies testbench control and configuration of Tx,Rx and monitor
  • Simplifies results analysis.
  • Runs in every major simulation environment.

Block Diagram

MIPI HTI Verification IP Block Diagram

Deliverables

  • Complete regression suite containing all the MIPI HTI testcases.
  • Examples showing how to connect various components, and usage of Tx,Rx and Monitor.
  • Detailed documentation of all class, task and function's used in verification env.
  • Documentation also contains User's Guide and Release notes.

Technical Specifications

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