MIPI DSI Tx Controller

Key Features

Interface with MIPI D-PHY following PHY Protocol Interface (PPI), as defined in MIPI Alliance Specification for D-PHY
Supports all commands defined in the MIPI Alliance specification for Display Command Set (DCS)
Transmission of all Command mode packets through the APB interface
Transmission of commands in low-power and high-speed during Video mode
Supports up to four D-PHY data lanes
Bidirectional communication and escape mode support through data lane 0
Supports non-continuous clock in D-PHY clock lane for additional power saving
Supports Ultra Low-Power mode with PLL disabled
ECC and Checksum capabilities
Support for End of Transmission Packet (EoTp)
Fault recovery schemes
3D transmission support
System interfaces: APB/DPI/DBI
Video pattern generator
Support video format up to 4Kp30
16-bit RGB
18-bit RGB
24-bit RGB
30-bit RGB
36-bit RGB (double clock rate required)
24-bit YCbCr 4:2:2
20-bit YCbCr 4:2:2 loosely packed
16-bit YCbCr 4:2:2
12-bit YCbCr 4:2:0
DSC24 compressed data