IP Catalog > Interface IP > Interconnect IP > MIPI IP > MIPI Controller IP > MIPI DSI IP > MIPI DSI Transmitter v1.2 Controller IP, Compatible with MIPI D-PHY & C-PHY

MIPI DSI Transmitter v1.2 Controller IP, Compatible with MIPI D-PHY & C-PHY

Overview

MIPI DSI transmitter IP is used to connect to up to two displays using the MIPI DSI-1 protocol. It supports video and command displays and can work in dual-display mode. Up to 4x 1.5Gbps D-PHY data lanes are supported. DPI and DBI are fully supported. DSI link can be switched from one mode to another (command to video or vice-versa) without resetting the IP. The behavior of this block is controlled via registers programmed using an APB interface (AMBA 3 compliant).

Key Features

  • MIPI Alliance Specification for Display Serial
  • MIPI display type 1, type 2, type 3 and type 4
  • Video mode (Non-Burst with Sync Pulses, Non-Burst with Sync Events and same for Burst mode).
  • TE feature (Tearing Effect) for command display
  • Power consumption modes (PLL on/off, D-PHY ULPS, optimized mode)
  • Supported display sizes: QQVGA (160 x 120) - 15/20/30/60 fps - 16-18 and 24 bits per pixels
  • QCIF (176x144), QCIF+ (176x208 and 176x220) - 15/20/30/60 fps - 16-18 and 24 bits per pixels
  • QVGA (320x240) - 15/20/30/60 fps - 16-18 and 24 bits per pixels
  • CIF (352x288), CIF+ (352x416 or 352x440) -15/20/30/60 fps - 16-18 and 24 bits per pixels
  • 1/2 VGA (320x480) and 2/3 VGA (640x320)-15/20/30/60 fps - 16-18 and 24 bits per pixels
  • VGA (640x480) - 15/20/30/60 fps - 16-18 and 24 bits per pixels
  • WVGA (800x480 - 848x480 -854x480 -852x480) - 15/20/30/60 fps - 16-18 and 24 bits per pixels
  • SVGA (800x600) - 15/20/30/60 fps - 16-18 and 24 bits per pixels
  • XVGA (1024x768) - 15/20/30/60 fps - 16-18 and 24 bits per pixels
  • Main interfaces: MIPI D-PHY PPI, APB system bus interface, 32-bit APB interface registers

Block Diagram

MIPI DSI Transmitter v1.2 Controller IP, Compatible with MIPI D-PHY & C-PHY Block Diagram

Deliverables

  • The MIPI DSI Tx Controller interface is available in Source and netlist products.
  • The Source product is delivered in plain text Verilog. If needed VHDL, SystemC code can also be provided.
  • Firmware code and Linux driver package
  • Documentation contains User's Guide and Release notes.

Technical Specifications

Foundry, Node
Independent, suitable to all 3rd party PHY's
Maturity
In Production
Availability
Immediate
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