MIPI D-PHY Universal IP in SMIC 130nm

Overview

The MXL-DPHY-UNIVERSAL-S-130 is a high-frequency low-power, low-cost, source-synchronous, Physical Layer compliant with the MIPI Alliance Standard for D-PHY.
The IP can be configured as a MIPI master or slave and consists of 5 lanes: 1 Clock lane and 4 data lanes.
The High-Speed signals have a low voltage swing, while Low-Power signals have large swing. High-Speed functions are used for High-Speed Data traffic while low power functions are mostly used for control.

Key Features

Consists of 1 Clock lane and 4 Data lanes
Complies with MIPI Standard 1.1 for D-PHY
Supports both high speed and low-power modes
80 Mbps to 1.0/1.5 Gbps data rate in high speed mode
10 Mbps data rate in low-power mode
High Speed Serializer and De-Serializer included
Low Power dissipation

Benefits

Supports both MIPI CSI-2 and MIPI DSI, as a transmitter and receiver
Silicon proven in SMIC 130nm

Block Diagram

Applications

Mobile
Displays
Cameras/Sensors
IoT
VR/AR/MR
Consumer electronics
Automotive

Deliverables

Specifications
GDSII
LVS netlist
LEF file
IBIS Model
Verilog Model
Timing Model
Integration Guidelines
RTL
Documentation
One year support

Technical Specifications

Foundry, Node

SMIC, 130nm

Maturity

Silicon Proven

Availability

Now

TSMC

Pre-Silicon: 40nm LP

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