The MIPI D-PHY v1.1 IP supporting speeds of up to 1.5 Gbps on TSMC 22nm process technology for SoC designs. The D-PHY IP is available on both TSMC’s industry-leading 22nm ultra-low power (22ULP) and 22nm ultra-low leakage (22ULL) process
technologies. TSMC 22nm ultra-low power (22ULP) is an ideal foundry technology for applications including image processing, digital TVs, set-top boxes, smartphones and consumer products in terms of its power, performance and area (PPA) optimization,
while its 22nm ultra-low leakage (22ULL) technology provides significant power reduction to support IoT and wearable device applications, where power is of paramount importance. MIPI D’Phy as a physical serial communicating layer is gaining traction in the today’s power hungry mobile and mobile related applications due to its low power consumption operation.
The D-PHY IP is also available as a Rx only IP for companies looking to save silicon area and further improve power consumption. The MIPI D-PHY IP is seamlessly integrated with its own DSI Tx and DSI Rx IP Cores as part of its Total MIPI Display IP Solution for wearables and IoT.
The Tx+ configuration has smaller area and standby current, as only two transmitters are need instead of the five transmitters that would be needed for a conventional 4 data-lanes Universal lane configuration.
The reduction in area is about 40% while standby power reduction is about 60%.
The MIPI D-PHY IP is proven on its own test chip on TSMC 28nm process, which has been licensed by multiple customers since 2016 and validated along with its CSI IP and DSI IP with 3rd Party VIP as a Total IP Solution.
The MIPI D-PHY IP is also available off the shelf on the TSMC 40nm, 28nm, 16nm and 12nm process technologies.
A D-PHY / C-PHY Combo HDK based on ASIC applications on TSMC 28nm process is also available to licensees of the DPHY IP or CPHY IP to prototype their Display or Imaging products before going to production.