MIPI D-PHY CSI-2 RX+ IP in TSMC 28HPC+ for Automotive Applications

Overview

The MXL-DPHY-CSI-RX+-T-28HPC+ is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specification for D-PHY v2.5. The PHY can be configured as a MIPI Slave supporting camera interface CSI-2. The PHY supports mobile, IoT, virtual reality, and automotive applications. The CSI-2 RX+ is a Mixel patented configuration that is optimized to support full-speed production and in-system testing while minimizing area and leakage power.

Key Features

Supports MIPI Alliance Specification for D-PHY Version 2.5
Consists of 1 Clock lane and 2 Data lanes
Embedded, high performance, and highly programmable PLL
Supports both low-power mode and high speed mode with integrated SERDES
80 Mbps to 1.5 Gbps data rate per lane in high speed D-PHY mode
10 Mbps data rate in low-power mode
Low power dissipation
Testability support including internal loopback
Calibrator for resistance termination

Benefits

Comprehensive embedded DFT features for allowing cost-effective high-volume manufacturing tests
Supports full-speed loopback testability with minimal area overhead for high-volume manufacturing tests
Embedded PLL with compact footprint used for generating high-speed clock during test modes and eliminate the need for an external PLL.
One transmitter is used to test multiple receivers to minimize area overhead
Two different loopback modes allow isolation of faults and defects
Analog test bus (ATB) for sensing internal analog voltages and currents

Block Diagram

Applications

Mobile
Cameras/Sensors
IoT
VR/AR/MR
Consumer electronics
Automotive

Deliverables

Specifications
GDSII
LVS netlist
LEF file
IBIS Model
Verilog Model
Timing Model
Integration Guidelines
RTL
Documentation
One year support

Technical Specifications

Foundry, Node

TSMC 28HPC+

Maturity

Silicon Proven

Availability

Now

TSMC

Pre-Silicon: 28nm HPCP

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