MIPI D-PHY
Key Features
- Compliant with the MIPI D-PHY spec v2.5
- Fully integrated hard macro with lane control and interface logic
- Up to 1.5 Gbps per lane with upgradable option to 2.5 Gbps per lane
- Supports PHY Protocol Interface (PPI)
- Low-power escape modes and ultra low-power state modes
Technical Specifications
Related IPs
- MIPI DPHY v1.2 RX 2 Lanes - TSMC 12FFCP 1.8V, North/South Poly Orientation
- MIPI DPHY v1.2 TX 2 Lanes - TSMC 12FFCP 1.8V, North/South Poly Orientation
- MIPI DPHY v1.2 TX 2 Lanes - TSMC 16FFC 1.8V, N/S, for Automotive, ASIL B Random, AEC-Q100 Grade 2
- MIPI DPHY v1.2 BD 4 Lanes - TSMC 16FFC 1.8V, North/South Poly Orientation
- MIPI DPHY v1.2 RX 2 Lanes - TSMC 16FFC 1.8V, North/South Poly Orientation
- MIPI DPHY v1.2 RX 4 Lanes - TSMC 16FFC 1.8V, North/South Poly Orientation