The Veriest Solutions MIPI CSI-2 v1.3 Transmit Controller facilitates transmission over a standard high-speed unidirectional serial interface between CSI-2 Transmitter and Receiver. The receiver is typically a host image processor. The transmitter is typically part of a camera device supplying image data.
CSI2 Tx v1.3 Transmitter supports two High-Speed serial interface options, D-PHY and C-PHY option. Depending on the chosen serial interface option, C-PHY 1.0 or D-PHY 1.2 is the physical layer block to which the MIPI CSI-2 Transmit controller interfaces for transmission.
CSI2 Tx converts received data into byte stream that follows the generic CSI2 protocol mapping rule. This IP calculates and appends an ECC or CRC value to packet header depending on the choice of the physical layer. For the payload of a long packet CSI2 Tx calculates its CRC value and appends to the packet as a footer and inserts packet Filler bytes after the Packet Footer, if needed. The packet is buffered in a FIFO and synchronized to the High-Speed Transmit clock domain and distributed to one or more data lanes depending on the lane distribution scheme set by the camera sensor. Packets are sent over D-PHY’s or C-PHY’s PPI interface depending on the PHY technology (D-PHY or C-PHY).
MIPI CSI2 v1.3 Transmit Controller
Overview
Key Features
- Compliant with the following MIPI specifications
- Camera Serial Interface (CSI-2) version 1.3
- D-PHY version 1.2
- C-PHY version 1.0
- CSI-2 interface on device facing side supports
- Connectivity to D-PHY through PHY Protocol Interface (PPI) Interface
- Connectivity to C-PHY through PHY Protocol Interface (PPI) Interface
- Configurable up to 8 data lanes for D-PHY option
- Configurable up to 4 data lanes for C-PHY option
- Maximum data rate of up to 2.5 Gbps per data lane for D-PHY option
- Maximum data rate of up to 2.5 Gsps (5714 Mbps) per data lane for C-PHY option
- Supports Unidirectional HS (High-Speed) Mode
- Data Synchronization from Core Clock Domain to High-Speed Transmit Clock Domain
- Support for Ultra Low Power Mode
- AMBA APB Slave interface for register configuration and control
- CSI2 Protocol Layer supports
- All primary and secondary CSI-2 data formats
- Short and Long packet formats for both physical layer options
- Check-Sum (CRC) Generation
- Error Correction Code (ECC) Generation for D-PHY option
- Up to 4 image streams using virtual channels
- Data Type and Virtual Channel Interleaving
- Camera Pixel Data Interface (CPI) supports
- Configurable Pixel Based User Interface (single, double, quad, octuple pixel wide)
- RAW and YUV formats
- Pixels to Byte Packing
- Packed Data Interface (PDI) supports
- 32/64 -bit Packed Data (recommended memory storage format)
- Generic or user-defined byte-based data types
Benefits
- Low Gate Count
- Low Power Consumption
- Fully Verified in with Advanced Function Verification
- Spyglass Lint Validated
- Standards Compliant
Block Diagram
Applications
- MIPI CSI2 Compliant Camera Sensor
Deliverables
- Synthesizable Verilog RTL
- Verilog test bench and test cases
- System Verilog verification environment and test cases
- Detailed block diagram and technical documents
Technical Specifications
Maturity
0.8 Release ready (for both, C-PHY and D-PHY option)
Availability
1.0 Release planned for May 2015