MIPI CSI-3 Rx Controller

Key Features

Hardware configurable compliance with MIPI specification CSI-3 Ver. 1.0
Provides error detection and retransmission, CPort / virtual channel detection, programmable data extraction, and embedded data separation
CPC support via register interface
Supported data types are
Generic 8bit Data
non-legacy YUV 4:2:0 8bit / 10bit with cosited chroma sampling
non-legacy YUV 4:2:0 8bit / 10bit with non-cosited chroma sampling
legacy YUV 4:2:0 8bit
YUV 4:2:2 8bit / 10bit
RGB 444 / 555 / 565 / 666 / 888 image data
RAW 6-bit / 7-bit / 8-bit / 10-bit / 12-bit image data
User defined 8-bit data
Compressed data types as defined in Annex A.2.6 of the CSI-3 Specification [MIPI1]
Max data rate 4.8 Gbit/s @ 300 MHz core clock
PHY Adapter
Hardware configurable support for Data and Control Interfaces to M-RX / M-TX Phys (RMMI) as specified in the Annex A of the M-PHY Specification [MIPI2]
Supports up to 4 receive (data) lanes and 1 transmit (control) lane
Number of used receive lanes automatically adjusted to connected peer device
Provides lane merging and clock domain crossing