MIPI C-PHY v2.0 /D-PHY v2.5 Combo IP in TSMC
Overview
MIPI D-PHY is a serial interface technology which is widely adopted in smartphones and other multimedia enabled mobile devices. To further improve throughput over bandwidth limited channel, the C-PHY is developed and is delivering 2.28 bits per symbol over three-wire trio. As a MIPI Alliance contributor and leading Interface IP provider, M31 provides a silicon-proven, low-power and low cost C-PHY/D-PHY combo IP on various process nodes. Users can configure the PHY into D-PHY mode or C-PHY mode to support different applications using the same PHY. It is compliant to the PPI interface which allows seamless integration with upside controllers for Camera Serial Interface (CSI-2) and Display Serial Interface (DSI) protocols.
Key Features
- Compliant with MIPI D-PHY v2.5 and C-PHY v2.0 specifications
- Supports MIPI DSI and CSI-2 protocols
- Supports HS data rates up to 6.5Gbps (6.5Gsps) per lane (per trio)
- Supports LS data rate of 10Mbps and Ultra-low power modes
- Supports D-PHY mode with 1 clock lane & up to 4 data lanes
- Supports C-PHY mode up to 3 trios for TX and 4 trios for RX
- Supports extra RX mode with 2 sets of 1 clock lane & up to 2 data lanes
- Supports Alternate Low-Power (ALP) mode
- Provides D-PHY swap function for clock and data lane
- Provides C-PHY swap function for trio
- Provides a stand-alone BIST module for at-speed mass production testing
- Certified with ASIL-B of ISO-26262
Block Diagram
Technical Specifications
Foundry, Node
5nm, 6nm, 7nm,12nm,16nm
Related IPs
- MIPI D-PHY / C-PHY Combo IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)
- MIPI C-PHY v2.0 D-PHY v2.1 RX 2 trios/2 Lanes in TSMC (N3E, N3P)
- MIPI C-PHY v2.0 D-PHY v2.1 RX 2 trios/2 Lanes in TSMC (N5A)
- MIPI C-PHY v2.0 D-PHY v2.1 RX 3 trios/4 Lanes in TSMC (N5, N3)
- MIPI C-PHY-D-PHY Combo PHY IP on TSMC 28nm HPC+
- MIPI D-PHY IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)