The Qualitas MIPI C-PHY is an advanced hard macro IP designed on Samsung 5nm process node. It adheres to MIPI C-PHY v2.1 standards, enabling high-bandwidth data transmission or reception off-chip at speeds up to 8Gsps per lane.
With integrated TX and RX capabilities on a single lane, it supports flexible role switching to optimize size efficiency as required. Supporting HS, LP, ALP, and CD modes, the C-PHY IP facilitates bi-directional data transmission in LP or HS mode. It also includes essential components such as I/O pads, ESD structures, and BIST features like loopback and scan for seamless integration.
MIPI C-PHY
Overview
Key Features
- Samsung Foundry 5nm low power enhanced (LN05LPE) CMOS device technology
- 1.2V±5%, 0.75/0.85V±5% power supply
- Fully supports MIPI C-PHY v2.1 HS/LP/ULPS TX/RX (Backward Compatible with previous versions)
- Supports 80-8000Msps (equivalent to 182.9-18,290Mbps) in C-PHY HS mode
- Global operation timing parameters control
Benefits
- Small area
- Low power consumption
- Supports both overdrive (0.85V) and normal (0.75V) power
- Lane configurable
- Built-in self-test feature capable of producing and checking PRBS random pattern
- Supports external loopback test
- Highly validated structure in various process nodes
Block Diagram
Applications
- Mobile, Automotive, AI, Security, AR/VR, etc
Deliverables
- FE-Common: MODEL, TWRAP, TB, LEF, LIBERTY, IPXACT, ATPG, SIPI
- BE-Common: CIR, GDS, DRC, LVS, DFMC
- DOC-Common: Datasheet, User Guide, Test Guide, Register Setting Guide, Supplement Guide, PLL Calculator
Technical Specifications
Foundry, Node
Samsung Foundry LN05LPE A00
Maturity
Silicon Proven
Availability
Now
Related IPs
- MIPI C-PHY v1.1
- MIPI C-PHY V1.1 TSMC 28nm HPC+
- MIPI CSI DSI C-PHY IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)
- MIPI CSI-2 controller Receiver v 2.1, Compatible with MIPI C-PHY v1.2 & DPHY v2.1.
- MIPI D-PHY / C-PHY Combo IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)
- MIPI C-PHY-D-PHY Combo PHY IP on TSMC 28nm HPC+