M8051 8-bit Microcontroller
Overview
The M8051 is a configurable soft-core implementation of the industry standard 8051 microcontroller that features a clock compatible twelve clocks per machine cycle architecture. This microcode-free design is software compatible (including instruction execution times) with industry standard discrete devices, having all their core features, and the additional features corresponding to the Intel 8051/8031/80C51BH/80C31BH/87C51 parts except that ONCE mode and Program Lock are not supported. The use of standard synchronous design methodology makes this core simple to integrate into both ASIC and FPGA SoC designs.
Key Features
- Binary and memory cycle compatible with Intel 8051, 8031, 80C51, 80C31, 80C31BH and 87C51
- 5-input, five level interrupt controller 32 GPIO ports
- Two 16-bit counter timers
- Classic 12-clock machine cycle implementation
- Up to 64Kbytes program and external data address spaces
- Full-duplex serial port
- Flexible interfacing options for external peripherals, including support for external SFRs, five of which may be bit- addressable
- Up to 256 bytes of internal data memory
- Support for memory banking extensions
- Power saving modes: powerdown and idle
- Program memory download mode
- Fully synthesizable and Scan test ready
Benefits
- The core RTL is highly configurable at compile time allowing users to implement only the features required by their application.
- Major configuration options include:
- Combined program and data address space or Harvard architecture
- Code memory size
- External data memory size
- Internal data memory size
- The M8051 offers two power saving states. In the idle state the CPU is stopped while the peripherals continue to run. In the powerdown state all clocks are stopped. These are implemented by dividing the core logic into several synchronous clock domains using optional clock gates. These reduce power consumption by 75% in the idle state and to leakage levels in the powerdown state. The microcontroller can be awoken from the idle state using interrupts.
- The core runs all standard 8051 binary code. Syntill8 recommends Keil C51 and IAR Systems compilers for code development.
Block Diagram
Deliverables
- VHDL '93 and Verilog 2001 RTL source code • VHDL and Verilog testbenches
- Demonstration assembly code
- Simulation scripts for Modelsim and Cadence • Example Synopsys synthesis compile scripts and SDC timing constraint files
- Example Mentor DFT and ATPG scripts
- Example netlist implementation with SDF files • Detailed product specification and a user guide containing implementation notes
Technical Specifications
Foundry, Node
any
Maturity
20+ years since first silicon
Availability
Now