IP Catalog > Interface IP > Interconnect IP > Serdes IP > LVDS serdes 4:28 channel decompression RX 8-150Mhz

LVDS serdes 4:28 channel decompression RX 8-150Mhz

Overview

FPD-LINK 24-bit color, 8-150Mhz Receiver
LVDS serdes 4:28 channel decompression RX 56-1050 Mbs x4

V-Trans 's FPD Link Receiver Macro is based on National Semiconductor openLDI specification v0.95 dated May 13th 1999 that allow the transfer of digital display data between a display source and a display device.
This receiver converts 4 LVDS, (low voltage differential signaling) data streams, into 24bits (single pixel) CMOS data plus 4 control signals (VSYNC, HSYNC, DE, and 1 user-defined signals), 28-bit CMOS .total.
At a maximum pixel rate of 150Mhz, LVDS data line speed is 1050Mbps, providing a total maximumbandwidth of 4.2Gb/s (525Mbytes per second).

Key Features

  • FPD-LINK Receiver (also available in 30bits color 150Mhz dual channel)
  • - 4:28 Data channel decompression up to 1050mb /lane
  • - Wide Frequency Range: 8 - 150MHz suited for VGA,SVGA,XGA and SXGA
  • - Narrow bus (10 lines) reduces cable size
  • - low EMI
  • - Supports Spread Spectrum Clock Generator
  • - On chip Jitter Filtering
  • - PLL requires No External Components
  • - 125mW(TYP)
  • - 3.3V Low Power CMOS
  • - Low Power CMOS Design
  • - Power-Down Mode
  • - Clock Edge Programmable for Transmitter
  • - Pin compatible with National DS 90C384/F386,THC63LVDM84B,

Deliverables

  • #NAME?

Technical Specifications

Availability
now
Silterra
Pre-Silicon: 180nm
TSMC
Pre-Silicon: 180nm G
Silicon Proven: 180nm G
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