IP Catalog > Interface IP > Interconnect IP > Serdes IP > LVDS serdes 28:4 channel compression TX 20-170Mhz

LVDS serdes 28:4 channel compression TX 20-170Mhz

Overview

LVDS serdes 28:4 channel compression TX 140-1190 Mbs x4
FPD-LINK Transmitter 24-bit color 20-170Mhz

This FPD Link Transmitter Macro is based on National Semiconductor openLDI specification v0.95 dated May 13th 1999 that allow the transfer of digital display data between a display source and a display device.

This transmitter converts 4 LVDS, (low voltage differential signaling) data streams, into up to 24 bits CMOS data plus 4 control signals (VSYNC, HSYNC, DE, and 1 user-defined signals).

At a maximum pixel rate of 170Mhz, LVDS data line speed is 1190Mbps, providing a total maximum bandwidth of 4.76Gb/s

Key Features

  • FPD-LINK Transmitter ( lowest pad count compare to other IP provider )
  • 28:4 Data channel compression up to 1190Mbs/channel
  • Wide Frequency Range: 20 - 170MHz (single channel) suited for VGA,SVGA,XGA and SXGA
  • Narrow bus (10 lines) reduces cable size
  • Variable LVDS output swing level from 200mv to 350mv for low EMI
  • Supports Spread Spectrum Clock Generator
  • On chip Jitter Filtering
  • PLL requires No External Components
  • 3.3V Low Power CMOS
  • Low Power CMOS Design
  • Power-Down Mode
  • Clock Edge Programmable for Transmitter
  • Pin compatible with National DS 90C385/F386

Deliverables

  • GDSII
  • LVS netlist
  • LIB timing
  • LEF abstract
  • Verilog/VHDL model
  • Datasheet
  • Application Note

Technical Specifications

Availability
now
Silterra
Pre-Silicon: 180nm
TSMC
Pre-Silicon: 180nm G
Silicon Proven: 180nm G
Request Info

Related IPs

×
Semiconductor IP