LPDDR5X/5/4X PHY in Samsung (SF4X)

Overview

Key Features

• Low latency, small area, low power
• Compatible with JEDEC standard LPDDR5X, LPDDR5 and LPDDR4X SDRAMs up to 8533 Mbps
• DFI 5.0 compliant interface to the memory controller
• DFI Frequency Ratio Support: DFI 1:1:4, 1:1:2 modes (DFICLK:CK:WCK)
• Flexible channel architecture
• 16- or 32-bit data path widths, supporting either a single 16-bit channel or two 16-bit channels
• 64-bit SDRAM support, supporting four 16-bit channels via two 32-bit PHYs
• Support for byte-mode DRAM devices for high-capacity systems
• Support for many DRAM packaging options:
• SDRAM components soldered directly to PCB
• Package on Package PoP devices
• PHY independent, firmware-based training using an embedded calibration processor
• Utilizes specialized hardware acceleration engines
• Supports:
• Command Bus Training (VREF and Delay)
• Write Leveling, Read Gate Training
• Write/Read Training:
• Per-bit DQS to DQ centering and per-bit deskew
• Per-rank VREFDQ training on DRAM DQ bits
• Periodic retraining for DRAM write (tDQS2DQ) and read (tDQSCK) drift
• IO calibration and ODT calibration
• Optional Decision Feedback Equalization (DFE) included for improved timing margins
• Support for up to 4 distinct trained states/frequencies to permit fast frequency changes
• Each trained state can have unique frequency, I/O drive, and ODT impedance settings
• Multiple inactive idle states including:
• DFI_LP Mode: most clocks and delay lines gated
• PHY Inactive: leakage only
• PHY Retention: Core power removed, most I/Os powered down, SDRAMs held in self-refresh
• Includes a low-jitter PLL for both PHY clock generation and SDRAM clock generation
• Only one PLL is required per DDR PHY
• Support for write/read preamble/postamble settings specified by JEDEC
• SW controllable DQ bit and AC bit swizzling
• Supports PHYs that go around a die corner and support for both East-West and North-South orientations
• Includes the PHY Utility Block (PUB)
• Soft IP Verilog design that includes PHY control features, such as read/write leveling and data eye training
• APB and JTAG interfaces for register access
• Test support:
• At-speed loopback testing on both the address and data channels
• Delay line BIST
• MUX-scan ATPG (stuck-at SCAN)
• PLL lock test
• ZQ calibration test
• Facilitates a JTAG register interface for easy test access
• Firmware-based 2D eye mapping diagnostic tool allows measuring 2D eye for every bit of the bus at both DRAM and host receivers
• Direct override programming available for all VREF, ODT, drive strength, and timing delays to facilitate debug and characterization
• Automotive grade PHYs in development

Benefits

• Supports JEDEC standard LPDDR5X, LPDDR5 and LPDDR4X SDRAMs
• Support for data rates up to 8533 Mbps
• Designed for rapid integration with Synopsys LPDDR5X/5/4X controller for a complete DDR interface solution
• DFI 5.0 controller interface
• PHY independent, firmware-based training using an embedded calibration processor
• Optional dual channel architecture which facilitates two independent channels in less area versus two independent PHYs
• Support for DFI-based low power modes and lower power sleep and retention modes
• Support for up to 4 trained states/ frequencies
• Flexible implementation to support Package-On-Package (PoP) or discrete DRAM-on-PCB systems with optimized PHY architecture
• Built-in anti-aging features to prevent effects of NBTI & HCI

Applications

• Smartphones and tablets
• Embedded mobile computing
• Ultraportable laptops / “Ultrabooks”
• Automotive
• Mobile multimedia
• Digital home and office
• Wireless connectivity

Deliverables

• Executable .run installation file which includes GDSII, LEF files, LVS netlists, .lib/.db timing models, Verilog model, DRC/LVS log files, I/O IBIS Model, I/O HSPICE netlist, parameterized Verilog top-level PHY netlist files, sample Verification Environment, PHY data book, physical implementation guide, app notes, verification guide, installation guide, and implementation checklist
• PUB includes Verilog code, Synthesis/ STA constraints and scripts, sample verification environment, and data book
• Implementation Guide, Application notes, and quick start manuals
• Firmware for training, ATE test and diagnostics
• DDR PHY compiler
• Optional deliverables include:
• Support for PHY emulation
• Signal integrity consulting services
• PHY hardening consulting services
• Subsystems consulting services
• IP Prototyping kit for FPGA-based prototyping

Technical Specifications