LPDDR5 Memory Model

Overview

LPDDR5 Memory Model provides an smart way to verify the LPDDR5 component of a SOC or a ASIC. The SmartDV's LPDDR5 memory model is fully compliant with standard LPDDR5 Specification and provides the following features. Better than Denali Memory Models.

LPDDR5 Memory Model is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

LPDDR5 Memory Model comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key Features

Supports LPDDR5 memory devices from all leading vendors.
Supports 100% of LPDDR5 protocol standard JESD209-5, JESD209-5A and JESD209-5B.
Supports all the LPDDR5 commands as per the specs.
Supports device density up to 32GB.
Supports X8 and X16 device modes.
Supports 2:1 and 4:1 CKR mode.
Supports all data rates as per specification.
Quickly validates the implementation of the LPDDR5 standard JESD209-5, JESD209-5A and JESD209-5B.
Supports burst length 16 and 32.
Supports programmable read/write latencies.
Supports BG, 8B and 16B bank organization modes.
Supports burst sequence.
Supports all mode register programming.
Supports write DBI and read DBI operation.
Supports write data mask operation.
Supports WCK2CK Sync operation.
Supports deep sleep mode.
Supports Multi rank.
Supports Optimized Refresh.
Supports Refresh Management Command.
Supports power down mode and self-refresh operation.
Supports frequency set point operation.
Supports programmable clock frequency of operation.
Supports following training modes.

Command bus training
WCK2CK leveling
WCK-DQ training
Enhanced RDQS training mode

Supports partial array self refresh segment masking.
Supports write clock free running mode.
Supports data copy low power function and write x operation.
Supports hybrid refresh mode and refresh credit mode.
Supports CA parity and ECC.
Checks for following

Check-points include power on, Initialization and power off rules,
State based rules, Active Command rules,
Read/Write Command rules etc.
All timing violations.

Supports callbacks for user to get command data on bus.
Protocol checker fully compliant with LPDDR5 Specification JESD209-5, JESD209-5A and JESD209-5B.
Constantly monitors LPDDR5 behavior during simulation.
Bus-accurate timing for min, max and typical values.
Models, detects and notifies the test bench of significant events such as transactions, warnings, timing and protocol violations.
Built in functional coverage analysis.
Supports Callbacks, so that user can access the data observed by monitor.

Benefits

Faster testbench development and more complete verification of LPDDR5 designs.
Easy to use command interface simplifies monitor control and configuration.
Simplifies results analysis.
Runs in every major simulation environment.

Block Diagram

Deliverables

Complete regression suite containing all the LPDDR5 testcases.
Complete UVM/OVM sequence library for LPDDR5 controller.
Examples showing how to connect and usage of Model.
Detailed documentation of all class, task and function's used in verification env.
Documentation also contains User's Guide and Release notes.

Technical Specifications

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