IP Catalog > Interface IP > Memory Interface IP > LPDDR IP > LPDDR5 IP > LPDDR5 Controller IP > LPDDR5 DFI Verification IP

LPDDR5 DFI Verification IP

Overview

LPDDR5 DFI Verification IP provides an smart way to verify the LPDDR5 DFI component of a SOC or a ASIC. The SmartDV's LPDDR5 DFI Verification IP is fully compliant with standard DFI Specification and provides the following features.

LPDDR5 DFI Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

LPDDR5 DFI Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key Features

  • Compliant with DFI version 5.0 Specifications.
  • Supports LPDDR5 devices compliant with JEDEC LPDDR5 SDRAM Standard JESD209-5, JESD209-5A and LPDDR5X(Draft).
  • Supports for Read data bus inversion.
  • Supports for Write data bus inversion.
  • Supports for DFI disconnect during training.
  • Supports for WCK Control interface.
  • Supports for 2:1 and 4:1 CKR mode.
  • Supports all data rates as per specification.
  • Supports write data mask operation.
  • Supports WCK2CK Sync operation.
  • Supports write clock free running mode.
  • Supports data copy low power function and write x operation.
  • Supports deep sleep mode.
  • Supports power down mode and self-refresh operation.
  • Supports frequency set point operation.
  • Supports programmable clock frequency of operation.
  • Supports following training modes.
    • Command bus training
    • WCK2CK leveling
    • WCK-DQ training
    • Enhanced RDQS training mode
  • Supports for input clock stop and frequency change.
  • Supports DRAM Clock disabling feature.
  • Supports Error signaling.
  • Supports all types of timing and protocol violations detection for timing parameters.
  • Constantly monitors DFI behavior during simulation.
  • Protocol checker fully compliant with DFI 5.0 Specifications.
  • Bus-accurate timing for min, max and typical values.
  • Notifies the test bench of significant events such as transactions, warnings.
  • Built in functional coverage analysis.
  • Supports callbacks, so that user can access the data observed by monitor.

Benefits

  • Faster test bench development and more complete verification of LPDDR5 DFI designs.
  • Easy to use command interface simplifies monitor control and configuration.
  • Simplifies results analysis.
  • Runs in every major simulation environment.

Block Diagram

LPDDR5 DFI Verification IP Block Diagram

Deliverables

  • Complete regression suite containing all the LPDDR5 DFI testcases.
  • Complete UVM/OVM sequence library for LPDDR5 DFI controller.
  • Examples showing how to connect and usage of Model.
  • Detailed documentation of all classes, tasks and functions used in verification env.
  • Documentation also contains User's Guide and Release notes.

Technical Specifications

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