IP Catalog > Memory Controller/PHY IP > DDR IP > DDR4 IP > DDR4 Controller IP > LPDDR4X/4/3/DDR4/3/3L PHY & Controller

LPDDR4X/4/3/DDR4/3/3L PHY & Controller

Overview

The DDR IP Mixed-Signal MR LPDDR4X/4/3/DDR4/3/3L Combo PHY provides turnkey physical interface solutions for ICs requiring access to JEDEC compatible SDRAM devices. It is optimized for low-power and high-speed applications with robust timing and small silicon area. It supports all LPDDR4X/4/3/DDR4/3/3L components in the market. The PHY components contain DDR-specialized functional and utility high-performance I/Os, critical timing synchronization modules (TSM), and low power/jitter DLLs with programmable fine-grain control for any SDRAM interface.

The comprehensive product portfolio also includes full GDS delivery, signal integrity and power integrity (SI/PI) analysis, verification models, prototyping support, and simulation tools. These offerings empower customers to accelerate development cycles, ensure robust performance, and stay ahead in the competitive landscape of high-performance memory solutions.

Key Features

  • Supports rates from 200Mbps up to:
    • 4266Mbps (LPDDR4X/4)
    • 3200Mbps (DDR4, even for WB-BGA)
    • 2133Mbps (LPDDR3/DDR3/3L)
    • 1066Mbps (LPDDR2/DDR2)
  • x8/x16/x32/x64 data bus width extendable
  • 1.2V/1.1V /1.5V JEDEC I/O standard, supporting 1.5V SSTL, 1.2V POD_12 I/Os, 1.1V LVSTL I/Os
  • Supports multiple types of training modes for stable working:
    • Driver Strength and ODT Auto Calibration Training
    • Command Bus Training
    • Rx DQS Gating Training
    • Write Leveling
    • Read/Write Training
    • Soft Rx Vref Scan
    • Auto Vref Training during Write Training
    • Periodic Re-training
    • Rx Eye Tracking, Compensation VT Drift
    • Voltage and Temperature Compensation for Rx Path
  • PVT compensation and timing calibration for all corner reliability
  • At-speed BIST for PAD and internal loopback modes
  • Supports multiple DFT methods: At-speed Scan, Stuck-at Scan, Boundary Scan
  • Various power-down modes for low-power including self-refresh support
  • Low-jitter PLL with small area, wide input frequency range and isolated analog supply, allowing for excellent supply rejection in noisy SoC applications

Benefits

  • Fully pre-assembled design, Drop-in hard macro to ease integration and speed time to market
  • Zero risk with robust ESD architecture
  • Extensive EDA tool support for various design and automation flow
  • Optional CKE retention mode permits VDD and all non-essential I/Os to be powered down while retaining the external SDRAMs in self-refresh mode
  • Comprehensive observation registers DFX and methods are available to facilitate customers in identifying issues during testing

Deliverables

  • Extensive documentation
  • Models
  • LIB
  • LEF
  • Place-and-route abstracts
  • LVS netlist
  • GDSII files

Technical Specifications

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