LPDDR SDRAM Controller
Overview
The LPDDR Synchronous Dynamic Random Access Memory (SDRAM) Controller is a general-purpose memory controller that interfaces with industry standard LPDDR memory devices/modules compliant with JESD209B, LPDDR SDRAM Standard, and provides a generic command interface to user applications. This IP core reduces the effort required to integrate the LPDDR memory controller with the remainder of the application and minimizes the need to directly deal with the LPDDR memory interface.
Key Features
- Interfaces to industry standard LPDDR SDRAM according to JESD209B
- Double-data rate architecture; two data transfers per clock cycle
- Bi-directional data strobe per byte of data (DQS)
- Programmable auto refresh support
- Data mask support – one mask per byte
- Power down and deep power down support
- Supports power-on initialization
- Supports re-initialization after a deep power down
- Dynamic I/O training after initialization
- Periodic I/O retraining after an auto refresh burst
- Dynamic memory clock power off during self refresh, power down and deep power down operations
- Supports single-port operation
- Supports full, half and quarter array self refresh
- Status register read support
- TCSR programmability through MRS
Block Diagram
Technical Specifications
Related IPs
- SDRAM DDRx & LPDDR4x Host Controller & PHY - TSMC 12nm 12FFC,FFC+
- LPDDR Controller IP
- SDRAM LPDDR5/4x/4/3/2 Host Controller & PHY - TSMC 16nm 16FFC,FF
- LPDDR Secure Controller supporting LPDDR5, LPDDR4 and LPDDR4X with Advanced Features Package
- LPDDR Secure Controller supporting LPDDR5X, LPDDR5 and LPDDR4X with Advanced Features Package
- LPDDR Controller ASIL B Compliant supporting LPDDR5X, LPDDR5 and LPDDR4X for Automotive Applications