Low-leakage LDO in TSMC 40 ULP to supply logic and analog domains (up to 5.5V input supply) with embedded Level Shifters
Applicable to automotive, industrial.
Designed for extended mission profile (aging report available)
Low-leakage LDO for logic and analog domains supply up to 5.5 Vin - High temperature (Grade 1, Tj=150°)
Overview
Key Features
- Low leakage current for best consumption in sleep mode
- High PSRR to supply analog loads
- Low quiescent
- Support input supply voltage up to 5.5V (Li-Ion, USB)
- Embedded Level Shifters
Technical Specifications
Foundry, Node
TSMC 40nm uLP
Maturity
Pre-silicon
TSMC
Pre-Silicon:
40nm
LP
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