Low (Active) Power Memory
Overview
The low power embedded SP SRAM utilizes a different architecture than typical memory compilers and is designed to be used in SoCs that require low active power consumption. It uses foundry provided bit cell and complements industry’s commercially available embedded memory IP offerings to provide maximum flexibility for designers to meet power and performance goals.
Key Features
- 35% lower active power
- 5% higher performance (at the same power level)
- Supports Retention and Power Down modes, with 65% lower leakage in Power Down mode
Deliverables
- Design Kit & Tape Kit:
- Verilog Model and Synopsys Model
- LVS netlist (CDL format)
- GDSII layout file (GDSII format)
- LEF view and Antenna LEF view
- Antenna CLF model and Mbist model
- Memory Manual and Document
Technical Specifications
SMIC
Silicon Proven:
55nm
LL
Related IPs
- Low Power Memory Compiler - Single Port SRAM - GF 22nm FDX
- Low Power Memory Compiler - 1-Port Register File Compiler - GF 22nm FDX
- I2C Controller IP – Slave, SCL Clock, Parameterized FIFO, APB Bus. For low power requirements in I2C Slave Controller interface to CPU
- AHB Low Power Subsystem - ARM Cortex M0
- OSC Crystal Oscillator Low Power Series
- Low Power PLL for TSMC 40nm ULP