Lossless JPEG Encoder - Up to 16-bit per Component Numerically Lossless Image & Video Compression

Overview

The LJPEG-E core from Alma Technologies implements the Lossless JPEG compression in a very compact, high-performance and stand-alone package. It supports up to 16-bit per component Numerically Lossless encoding and is ideal for image and video compression applications where bit-by-bit accurate reproduction of an image is essential, while the amount of compression needed is very low.

The LJPEG-E conforms to the spatial (sequential) lossless encoding mode (SOF3) of the ISO/IEC 10918-1 standard (CCITT T.81 recommendation). Rather than the Discrete Cosine Transform (DCT) functions used for lossy JPEG compression - which introduce round-off errors - Lossless JPEG employs a predictor function and compresses images by encoding the prediction error with no information loss.

The core is designed with simple, fully flow-controllable and FIFO-like, streaming input and output interfaces. Being carefully designed, rigorously verified and silicon-proven, the LJPEG-E is a compact, reliable and easy-to-use and integrate IP.

Key Features

  • ISO/IEC 10918-1 (Annex H) Compliant Lossless JPEG Encoder
    • Up to 64K x 64K image resolution
    • 1, 2 or 3 (4:4:4 only) image components
    • 2-16 bit per image component
    • Up to 4 programmable Huffman Tables
    • Programmable Restart Interval
    • Programmable Point Transform function
    • Complete, standalone Lossless JPEG stream output
  • Limitations with Respect to the ISO/IEC 10918-1 Standard
    • Up to 3 image components are supported (Nf field of the SOF3 marker segment = 1 or 2 or 3)
    • Single-scan encoding (Only one SOS marker segment, with Ns field = Nf)
    • No DNL marker insertion (Y field of the SOF3 marker segment > 0)
    • Fixed parameters
      • No sub-sampling (Hi and Vi fields of the SOF3 marker segment = 1)
      • Prediction function is fixed to the left-hand predictor (Ss field of SOS marker segment = 1)
    • Ease of Integration
      • Single clock cycle per sample encoding throughput
      • Simple, microcontroller like, programming interface
      • High-speed, flow controllable, streaming I/O data interfaces
        • Simple and FIFO like
        • Avalon-ST compliant (ready latency 0)
        • AXI4-Stream compliant
      • CPU-less, standalone operation
    • Trouble-Free Technology Map and Implementation
      • Fully portable, self-contained RTL source code
      • Strictly positive edge triggered design
      • D-type only Flip-Flops
      • Fully synchronous operation
      • No special timing constraints required
        • No false paths
        • No multi-cycle paths

    Block Diagram

    Lossless JPEG Encoder - Up to 16-bit per Component Numerically Lossless Image & Video Compression Block Diagram

    Deliverables

    • Clear text VHDL or Verilog RTL source for ASIC designs, or pre-synthesized & verified Netlist for Altera, Lattice, Microsemi and Xilinx FPGA and SoC devices
    • Release Notes, Design Specification and Integration Manual documents
    • Bit Accurate Model (BAM) and test vector generation binaries, including sample scripts
    • Self checking testbench environment, including sample BAM generated test cases
    • Simulation and sample Synthesis (for ASICs) or Place & Route (for FPGAs) scripts

    Technical Specifications

    Maturity
    Silicon Proven
    Availability
    NOW
×
Semiconductor IP