The AH1001_LEQ LMS Adaptive Channel Equalizer (LEQ) FPGA core provides a 17-tap Least Mean Squares (LMS) signed-error adaptive Channel Equalizer in a single module. The core provides automatic adaptive equalization of channel distortion and multipath effects for single-carrier communication systems.
LMS Adaptive Channel Equalizer
Overview
Key Features
- 17-tap T-spaced complex-arithmetic LMS signed-error Channel Equalizer
- Adaptation bandwidth control (mu, step size)
- Leakage rate control (forgetting factor)
- Coefficient hold control (adaptation freeze)
- Coefficient reset control
- IQ channel and cross-tap coefficient readout
- Center taps are fixed for phase stability
- Multiplexed architecture minimizes resource utilization. Requires only 17 DSP48 blocks.
- Clock rates up to 548 MHz supported
- Symbol rates up to 1/5 of clock rate
Benefits
- Restores link performance in the presence of common channel impairments such as multipath reflections, cable tilt, filter distortion, or other effects
- Includes full readout capability of complex tap coefficient values for channel analysis
- Low complexity for hardware and power efficiency
- Adaptation rate control provides flexibility
Block Diagram
Applications
- Single-carrier Communication Links
- Terrestrial Microwave Links
- Cellular Backhaul
- Cable Modems
- Point-to-Point or Point-to-Multipoint systems
Deliverables
- Product License
- EDIF or NGC core
- Verilog Test Bench
- Supporting Matlab/Octave code for test vector generation and analysis
- Verilog simulation model
- Product Documentation
Technical Specifications
Maturity
Field-proven
Availability
Now