Link Protocol Engine

Key Features

• Fully compliant Infiniband architecture based on Infiniband Trade Association (IBTA) 1.0.a Specifications.
• Compliance to Test Suites as provided by University of New Hampshire Inter-Operability Lab.
• Full Duplex Independent Transmit and Receive Data Path controlled by Link State Machine.
• Optimized for the use in Host and Target Channel Adapters.
• Supports all Management and Data Packets.
• Supports all Transport Services and Raw Packets.
• Four data Virtual Lanes (VL) plus Management Virtual Lane (MVL) support.
• Provides credit based Link level flow control to handle Pipelined data.
• Has a 1X (Single Link with Receive and Transmit) physical layer independent LINK-PHY Interface
• PHY Interface Data Rate for 1X is 2 GBPS LINK-PHY; 4 GBPS for Full-Duplex
• Distinct 32-bit data lines for transmit and receive.
• Supports max up to total 512 Kbytes of external buffer memory for transmit and receive.
• External Buffer memory can be fine tuned by user as per its need of application.
• Single clock domain throughout the system.

Benefits

• Clock Frequency: 74.6MHz for FPGA (Standard: 62.5 MHz)

Deliverables

• Fully synthesizable Register Transfer Level (RTL) Verilog HDL core.
• Test Bench Environment Verilog
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Technical Specifications