LDO Voltage Regulator, 250 mA, Adjustable 0.45 V to 0.9 V Output
Overview
The LDO IP is a 1.2V low-quiescent-current adjustable output voltage Low-Drop-Out (LDO) Linear Regulator implemented in the TSMC 3nm N3P CMOS process technology. Its low sleep current, 250 mA maximum current, output voltage adjustability and precision make it especially suitable for use as an integrated voltage regulation source for subsystems implemented in analog, digital, mixed-signal and RF ASICs and SoCs.
Key Features
- TSMC 3nm FinFET process
- Input voltage: 1.2 V
- Output voltage range: 0.45 V to 0.9 V
- Vout adjustable in 50 mV increments
- Load current: 250 mA (max)
- PSRR:36 dB @ < 1 KHz
- PSSR: 12 dB @ > 10 MHz
- < 50 mV undershoot/overshoot for load transients 1 A/ns
- Compact area
- Capless stable operation
- Functional from -40°C to 125°C
Block Diagram
Deliverables
- SPICE netlist
- GDSII
- Behavioral Model
- IP Datasheet
- User’s Guide
Technical Specifications
Foundry, Node
TSMC, 3nm
Maturity
Silicon Proven
Availability
Now
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