The Scalable LDO (Low Drop Out) Regulator macro addresses typical SOC power supply and other voltage regulation needs in a fully integrated easy-to-use macro.
The LDO macro includes an internal bandgap style voltage reference circuitwhich is used as a reference to compare the voltage supplies against. Alternately, the output voltage may be programmed to be proportional to the input supply or other reference voltage.
The LDO is available for use in various current levels, load variability and noise sensitivity, in integer multiples of the “unit LDO” described in Table 1.
Specifications Description Symbol Min Typ Max Units LDO Power Voltage Input VIN 0.8 - 1.32 V LDO Power Voltage Output VOUT 0.55 - 1.2 V LDO Power Voltage Output Extended VOUT 0.4 - - V VOUT Precision (untrimmed) -3.5 - 3.5 % VOUT Precision (post-trim) -1.5 - 1.5 % VOUT Slew Rate 30 mV/us Output Capacitance CL 0.1 - - µF Total Load Current IL 0.5 2 7.5 A Total Load Current Bypass Mode IL - - 9 A Startup Time - - 10 us Voltage Step Resolution - 5 - mV Clock Frequency FREF 100 - TBD MHz LDO VOUT Ripple - - 15 mVpp LDO VOUT Droop - - 50 mV Dropout Voltage 50 100 - mV Load Regulation - - 2 mV/A Supply Rejection PSRR 10 - - dB Total area of macro A 0.03 sq.mm Total Power IDD 180 uA Operational Voltage (Digital) VDIG 0.7 0.75 0.8 V Operational Voltage (Analog) VANA 1.14 1.2 1.32 V Operational Temperature TOP 0 105 125 C Table 1: Specifications COPYRIGHT © 2023, Analog Bits Inc., All Rights Reserved Scalable LDO Regulator Datasheet (CLN3A) VIN ENA BYPASS CLK FB LDO VOUT BG_SEL VOUT_SEL[7:0] CONFIG[3:0] Figure 1: Block Diagram Pin Description Pin Type Function VDD Power Core Power (0.75V) VDDA Power Analog Power (1.2V) VIN Power Input Power (1.2V) VOUT Power Output Power (0.75V) VSS Power Core Ground (0V) ENA Input LDO Enable BYPASS Input LDO Bypass CLK Input External Reference Clock FB Input LDO Feedback BG_SEL Input BG reference select VOUT_SEL[7:0] Input Output voltage select Trim can be applied as an offset to the VOUT_SEL code CONFIG[3:0] Input Reserved Table 2: Pin Description Deliverables and EDA Design Views Front-end Design Views (with NDA) Back-end Design Views (with License Agreement) Verilog Model GDSII stream file Synopsys (LIB) CDL/Spice netlist Footprint (LEF) format Application Notes inclusive of design integration guidelines (PDF) Datasheet (PDF) Table 3: List of Deliverables