Kasumi Encryption Core

Overview

The KSM1 core implements Kasumi encryption in compliance with the ETSI SAGE specification. It processes 64-bit blocks using 128-bit key.
Basic core is very small (5,500 gates). Enhanced versions are available that support various cipher modes (ECB, CBC, OFB, CFB, CTR.
The design is fully synchronous and available in both source and netlist form. Test bench includes the Kasumi test vectors.
KSM1 core is supplied as portable Verilog (VHDL version available) thus allowing customers to carry out an internal code review to ensure its security.

Key Features

Encryption using the Kasumi Block Cipher Algorithm
Since all practical uses of Kasumi utilize only the encryption operation, decryption is not part of the core
High throughput: up to 3 Gbps in 65 nm process
Small size: from 5.5K ASIC gates
Satisfies ETSI SAGE Kasumi specification and 3GPP TS 35.202
Processes 64-bit data blocks
Use 128-bit key
Completely self-contained: does not require external memory
Available as fully functional and synthesizable Verilog, or as a netlist for popular programmable devices and ASIC libraries
Deliverables include test benches

Benefits

Smallest Kasumi core on the market

Block Diagram

Applications

Secure mobile phone communications
3GPP UMTS algorithms f8 and f9
A5/3 implementation

Deliverables

HDL Source Licenses
- Synthesizable Verilog RTL source code
- Verilog testbench (self-checking)
- Test vectors
- Expected results
- User Documentation
Netlist Licenses
- Post-synthesis EDIF
- Testbench (self-checking)
- Test vectors
- Expected results

Technical Specifications

Foundry, Node

Technology independent

Availability

Off-the-shelf

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