IP Catalog > Interface IP Cores > Other > JTAG Verification IP

JTAG Verification IP

Overview

The JTAG Verification IP provides an effective & efficient way to verify the components interfacing with the JTAG interface of an ASIC/FPGA or SoC.​

The JTAG VIP is fully compliant with Standard JTAG Version IEEE 1149.1-2013 JTAG specification from JEDEC. This VIP is lightweight with an easy plug-and-play interface so that there is no hit on the design time and the simulation time.

Key Features

  • Supports IEEE 1149.1-2013 JTAG Protocol Standard.
  • DUT can be:
    • Master
    • Slave
  • Configurable instruction register.
  • Configurable data register width.
  • Dynamically configurable data register width.
  • User-defined instructions.
  • User-defined data registers.
  • Reports current state of TAP finite state machine.
  • Support for both public and private instructions.
  • User-defined BFM instructions.
  • Support for all Test Access Port (TAP) pins.
  • Internal and external clock and reset modes.
  • Supports constraints randomization.
  • Status counters for various events on the bus.
  • Supports callbacks for a user to define a custom instruction decoder.
  • Supports callbacks for a user to get a callback on each state of the TAPcontroller.
  • Support all types of timing and protocol violation detection.
  • Functional coverage for checking all possible stimulus checking.
  • Protocol-aware debug.

Benefits

  • Available in native SystemVerilog(UVM/OVM/VMM) and Verilog
  • Unique development methodology to ensure the highest level of quality.
  • Availability of Compliance & Regression TestSuites.
  • 24X5 customer support
  • Unique and customizable licensing models
  • Exhaustive set of assertions and cover pointswith connectivity example for all thecomponents.
  • Consistency of interface, installation,operation, and documentation across all over.

Deliverables

  • JTAG Driver BFM/Agent
  • JTAG Monitor & Scoreboard
  • JTAG Controller BFM/Agent
  • Test-Bench Configurations
  • Test Suite (Available in Source code)
    • Basic Protocol Tests
    • Directed & Random Tests
    • Assertions & Cover Point Tests
  • Integration Guide, User Manual, and Release Notes

Technical Specifications

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JTAG Verification IP
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