The Synopsys IP solutions for the ARM® AMBA® interconnect include synthesizable IP, verification IP (VIP) and automated assembly with Synopsys’ coreAssembler tool. The Synopsys IP for the AMBA interconnect allows designers to rapidly integrate infrastructure components into their systems-on-chip (SoC)
and verify results with less risk and a reduced design cycle. Complementing the synthesizable IP is the VIP for AMBA interconnect, which includes the master, slave and monitor, providing designers with a quick and efficient way to verify AMBA interconnect-based SoCs. The Synopsys coreAssembler tool provides an automated method for assembling and configuring IP in a subsystem and develops an initial verification testbench for both the AMBA 2.0 and AMBA 3 AXI, AMBA 4
AXI and ACE-Lite protocol-based designs. This automation reduces the complexity of designing AMBA-based subsystems and improves overall productivity for faster time-to-results.
IP Solutions for the AMBA Interconnect
Overview
Benefits
- High-performance, low-latency interconnect fabric for AMBA 3 AXI and AMBA 4 AXI with ACE- Lite support
- Configurable standalone pipelining stage for AMBA 3 AXI and AMBA 4 AXI subsystems
- Configurable multi-layer interconnection matrix
- Bridge from AMBA 3 AXI/AMBA 4 AXI to AMBA 2.0 AHB enables easy integration of legacy AHB designs with newer AXI systems
- Configurable high-performance interface from an AHB master to an AXI slave
- Simplifies the connection of third party/custom master or slave controllers to any AMBA 3 AXI/AMBA 4 AXI fabric
- Configurable vectored interrupt controllers for AHB or APB bus systems
- Verification IP for AMBA 2 AHB/ APB and AMBA 3 AXI/AMBA 4 AXI
Applications
- Imaging processing
- Motion processing
- Speech recognition
- Signal processing
- Filtering
Technical Specifications
Maturity
Available on request
Availability
Available
Related IPs
- Chiplet Interconnect - Die-to-die interconnect IP solutions for advanced and standard packaging applications
- SPI Slave IP transfers to/from a AMBA APB, AXI, or AHB Interconnect
- I2C Controller IP – Slave, SCL Clock only, principally for configuring registers in mixed-signal ICs with low noise or low power requirements
- SPI Controller IP- Master/Slave, Parameterized FIFO, AMBA APB / AHB / AXI Bus
- SPI Controller IP- Master-only, Parameterized FIFO, AMBA APB / AHB / AXI Bus
- I2C Controller IP – Slave, SCL Clock, Parameterized FIFO, APB Bus. For low power requirements in I2C Slave Controller interface to CPU