Interrupt controller with APB interface
Key Features
- APB bus
- Support up to 32 fast interrupt (FIQ) inputs by configuration
- Support up to 32 standard interrupt (IRQ) inputs by configuration
- Provide both edge and level triggered interrupt source with positive and negative directions.
- Support de-bounce circuit for interrupt input sources by configuration
Technical Specifications
Related IPs
- Compact Flash host interface controller with APB interface.
- I2C Controller IP – Slave, SCL Clock, Parameterized FIFO, APB Bus. For low power requirements in I2C Slave Controller interface to CPU
- Real-Time Clock with APB Interface
- Watchdog Timer with APB Interface
- Timer/Counter with APB Interface
- I2C Controller IP – Slave, Parameterized FIFO, APB Master Interface (I2C2APB)