IP Catalog > Analog IP > Clocking IP > PLL IP > General Purpose PLL IP > Input 2MHz~16MHz, output 16~72MHz and 72MHz~200MHz, 1.08~1.32V PLL; UMC 55nm Low Power Process.

Input 2MHz~16MHz, output 16~72MHz and 72MHz~200MHz, 1.08~1.32V PLL; UMC 55nm Low Power Process.

Overview

Input 2MHz~16MHz, output 16~72MHz and 72MHz~200MHz, 1.08~1.32V PLL; UMC 55nm Low Power Process.

Technical Specifications

Foundry, Node
UMC 55nm
Maturity
Pre-Silicon release
UMC
Pre-Silicon: 55nm
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