The I3C Advanced Target is a highly configurable I3C Target that can be used in microcontroller based environments to provide I3C connectivity to any device. It can be configured in a number of different ways to allow the core to use the minimum amount of logic to reduce both area (cost) and power.
I3C V1.1 Advanced Target
Overview
Key Features
- Highly configurable core that allows customer to
- minimize unneeded logic
- Compliant with MIPI I3C V1.1.1
- Compliant with MIPI I3C Basic V1.1.1
- Dynamic addressing
- Single Data Rate (SDR)
- Error detection types (TE0-TE5)
- Advanced I3C features
- HDR-BT with up to 100 Mbps bandwidth
- Multilane with 1, 2, or 4 SDA lanes
- Hot join
- In-band interrupts
- Timing Control
- Asynchronous Mode 0
- Synchronous Mode
- High-speed mode (HDR-DDR)
- Group addressing
- Target reset
- All Common Command Codes (CCCs) supported
- AMBA APB (v3) application interface
- Memory mapped registers
- DMA, flow control features
- FIFO options
- Internal 2-byte ping-pong buffer
- Internal FIFO (or 32 words for HDR-BT mode)
- Static I2C address support
- Legacy I2C coexistence, including I2C messaging
- Support for I2C pads with 50ns glitch filter
Block Diagram
Applications
- IoT Edge Devices
- Industrial Sensors
- Small Controllers
- Mixed Signal Digital - MEMS
- Smart Sensors
- Smart Lighting
- Temperature, Pressure, Acceleration Monitors
- Personal Health Monitors
- I3C Connected Devices
Deliverables
- Verilog RTL source code
- Test bench with test suites
- Documentation including User's Guide and Integration Guide
- Technology-independent synthesis constraints