I2C IO Pad Set
Overview
The I2C library provides the bidirectional I/O for two-line serial communication per Rev. 4 of the I2C-bus industry specification. The design is compatible with Standard-mode, Fast-mode, and High-speed mode I2C operating modes. This library is offered as a supplement to the IO libraries provided by Aragio Solutions
Key Features
- • Supported I2C operating modes:
- o Standard-mode (Sm) – 100 Kbps data rate
- o Fast mode (Fm) – 400 Kbps data rate
- o Fast mode (Fm+) – 1.0 Mbps data rate
- • Open drain operation only (floating NWELL with PMOS used for ESD protection only)
- • Built-in output slew rate control to meet I2C Tof minimum of (20 x VDDP/5.5V) ns
- • Output enable
- • Receiver enable
- • ESD protection uses snap-back devices (no diode to the positive power supply)
- • Standard LVCMOS input thresholds (no hysteresis)
- • Staggered I/O CUP implementation
- • Power-on sequencing independent design with Power-On Control
- • DVDD = 2.7V to 3.63V and VDD = 0.85V to 1.1V
- • Pad VDDP (power supply reference for Output) = 2.7V to 3.63V independent of DVDD.
- • The circuit consumes no DC supply current in the static state
Deliverables
- a. Physical abstract in LEF format (.lef)
- b. Timing models in Synopsys Liberty formats (.lib and .db)
- c. Calibre compatible LVS netlist in CDL format (.cdl)
- d. GDSII stream (.gds)
- e. Behavioral Verilog (.v)
- f. Layout Parasitic Extraction (LPE) SPICE netlist (.spice)
- g. Databook (.pdf)
- h. Library User Guide - ESD Guidelines (.pdf)
Technical Specifications
Foundry, Node
GLOBALFOUNDRIES 28nm SLP
Maturity
Silicon Proven
Availability
Available Now
GLOBALFOUNDRIES
Silicon Proven:
28nm
HPP
,
28nm
LPH
,
28nm
SLP
,
40nm
LP
,
65nm
,
65nm
LP
,
65nm
LPe
TSMC
Silicon Proven:
65nm
G
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