I2C Controller IP – Master, Parameterized FIFO, Avalon Bus

Overview

The DB-I2C-M-AVLN Controller IP Core interfaces a microprocessor via the Avalon Bus to an I2C Bus. The I2C is a two-wire bidirectional interface standard (SCL is Clock, SDA is Data) for transfer of bytes of information between two or more compliant I2C devices, typically with a microprocessor behind the master controller and one or more slave devices.

The DB-I2C-M-AVLN is a Master I2C Controller that controls the Transmit or Receive of data to or from slave I2C devices. In an Altera FPGA, typically, the microprocessor is a NIOS II processor, but can be any FPGA embedded processor. Figure 1 depicts the system view of the DB-I2C-M-AVLN Controller IP Core embedded within an FPGA integrated circuit device.

The DB-I2C-M-AVLN Controller IP Core targets embedded processor applications with higher performance algorithm requirements. While most I2C controllers require high processor interaction involvement, the DB-I2C-M-AVLN contains a parameterized FIFO and Smart Control for the processor to off-load the I2C transfer to the DB-I2C-M-AVLN Controller. Thus, while the DB-I2C-M-AVLN is busy, independently controlling the I2C Transmit or Receive transaction of data, the processor can go off and complete other tasks. Note that the Master only capability of the DB-I2C-M-AVLN adds to its small VLSI footprint requirements.

Key Features

Master I2C Controller Modes:
- Master – Transmitter
- Master – Receiver
Supports four I2C bus speeds:
- Hs-Mode (3.4+ Mb/s)
- Fast Mode Plus (1 Mbit/s)
- Fast Mode (400 Kb/s)
- Standard Mode (100 Kb/s)
Parameterized FIFO memory for off-loading the I2C transfers from the processor:
- Targets embedded processors with higher performance algorithm requirements, by the I2C Controller independently controlling theTransmit or Receive of bytes of information buffered to and from a FIFO.
Enhanced system-level features & integration capabilities:
- CPU Interface via parameterized FIFO with support for APB / AHB / AXI / AXI-lite / Avalon / Qsys interconnect fabrics
- Enhanced SCL / SDA spike filtering capabilities
- Enhanced Repeated Start capabilities
Enhanced system-level features & integration capabilities (Optional):
- DMA transfer between the I2C Bus & Memory (SDRAM / SRAM / FLASH)
- Direct interface to user Registers within ASIC / ASSP / FPGA device, for Master/Slave transfer across the I2C Bus
- Remote Configuration of a Digital Blocks’ I2C Slave by an I2C Master
I2C compliant features:
Multi-Master, Clock Synchronization, Arbitration, Repeated Start, 7/10-bit addressing, & General Call Addressing
Compliance with Altera Avalon and I2C specifications:
- Compliance with Avalon Memory Mapped Interface Specification (MNL-AVABUSREF-3.2)
- Philips/NXP – The I2C-Bus Specification, Version 2.1, January 2000 and UM10204 Rev 7 – 1 Oct 2021
Fully-synchronous, synthesizable Verilog or VHDL RTL core, with rising-edge clocking, no gated clocks, and no internal tri-states, for easy integration intoFPGA or ASIC design flows.

Block Diagram

Deliverables

The DB-I2C-M-AVLN is available in synthesizable RTL Verilog or VHDL or a technology-specific netlist for FPGAs, along with synthesis scripts, a simulation test bench with expected results, datasheet, and user manual.
The DB-I2C-M-AVLN comes along with example C code software for controlling Transmit and Receive Transactions in the Eclipse-based Nios® II Integrated Development Environment (IDE).

Technical Specifications

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