I2C Dual mode IP ( master and slave mode) with APB interface to support the standard I2C Bus Protocol and APB5 Interface on the Application side. It is an Inter Integration Circuit IP that provides a simple way to talk between integrated circuits by using 4 wires: two SCL (Serial Clock) lines and two SDA (Serial Data) lines. These lines are divided into input and output lines. This IP acts as a transmitter as well as a receiver.
I2C Controller
Overview
Key Features
- Configuration: Controller and Target
- Programmable via Host interface
- Only one configuration will be active at a given time
- Different bus modes:
- a. Standard Mode (0 to 100 kbit/s)
- b. Fast Mode (<= 400 kbit/s)
- c. Fast Mode Plus (<= 1000 kbit/s)
- d. High Speed Mode (<= 3.4 Mbit/s)
- Target Addressing: 7bit
- Level or Edge Interrupt defined via parameter
- Standard APB5 Interface used for Host interface
- Separate clock domain for IP Core functionality and Host Interface.
- a. Parameter used to select same clock or different clocks for IP Core functionality and Host Interface.
- Buffers on both Transmit and Receive path with parameterizable depths.
- DMA interface for Host to DMA data into/from the IP Buffers.
Benefits
- Dual mode IP (master and slave mode).
- Supports different modes of transfer .
- Supports DMA interface also .
- Separate clock domain for IP Core functionality and Host Interface.
- I2C can communicate with 128 different slaves since it supports 7 bit addressing mode (2 ^7 = 128).
Block Diagram
Deliverables
- Design IP
- integration manual
- Design Constraints
- Lint CDC Waivers
Technical Specifications
Availability
NOW