HSSTP TX PHY 5nm Samsung Foundry

Overview

The sf_hsstp13b2t_ln05lpe is a hard macro IP implementing the ARM HSSTP PHY Layer for Samsung's 5nm process technology. This IP enables SoCs to serially transmit high bandwidth data off-chip, achieving speeds up to 6Gbps per lane.
It offers variable data rates with a fractional-N (Frac-N) RO PLL and configuration options for 1 or 2 lanes, I/O pads and ESD protection are included along with at-speed BIST and scan test functionalities for stramlined integration and reliable performance.

Key Features

Samsung Foundry 5nm (SF5A) CMOS device technology
1.8V±5%, 0.75V±5% power supply
Fully supports ARM HSSTP v6.0
Supports 1.5/3/6Gbps data rates
Two hybrid mode driver-lane for AC coupled links
RO PLL to support multiple data rates for HSSTP

Benefits

Low power consumption, small area
1-lane or 2-lane configurable
At-speed BIST and SCAN for Design For Test (DFT)
Automatic resistor calibration
Critical analog nodes and calibration code observability

Block Diagram

Applications

High performance embedded microprocessor

Deliverables

FE-Common: MODEL, TB, LEF, LIBERTY, IPXACT, ATPG, SIPI
BE-Common: CIR, GDS, DRC, LVS, DFMC
DOC-Common: Datasheet, User Guide, Test Guide, Register Setting Guide

Technical Specifications

Foundry, Node

Samsung Foundry SF5A

Maturity

Silicon Proven

Availability

Now

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