The sf_hsstp is a soft macro IP designed for the ARM HSSTP Link Layer. It enables SoCs to utilize serial transmit ports for higher trace data bandwidth.
This IP is fully compliant with the ARM HSSTP Standard Specification v6.0, featuring support for a TPIU 32-bit trace data interface and internal bandwidth control. For optimal functionality, the HSSTP Link pairs effectively with the sf_hsstp13b2t_ln05lpe.
HSSTP Link
Overview
Key Features
- Compliant to ARM HSSTP Standard Specification v6.0
- Support Xilinx Aurora Protocol Specification
- Support STP simplex operation
- Support internal bandwidth control
- Support TPIU 32bit tracedata interface
- Support User Flow Control frame
Benefits
- Low power consumption
- Lower ASIC pin count
- Increase possible bandwidth and reduce the silicon area
Block Diagram
Applications
- High performance embedded microprocessor
Deliverables
- FE-Common: Encrypted RTL, Synthesis Scripts, TB
- DOC-Common: Datasheet, User Guide
Technical Specifications
Maturity
Silicon Proven
Availability
Now
Related IPs
- ARM HSSTP PHY with Link Layer
- Link Layer Controller
- Link Protocol Engine
- APB Fundamental Peripheral IP, Serial Interface controller for multiple frame formats, SSP (by TI), SPI (by Motorola), Microwire (by NS), I2S (by Philips), AC - link (by Intel) and SPDIF (by Intel), Soft IP
- Synchronous Data Link Controller
- PCI Express PHY serial link PIPE Transceiver IP cell/hard macro