I2C Controller IP – Master, Parameterized FIFO, Hs-Mode (3.4 Mbps) AXI/AHB/APB/Avalon Buses

Overview

The DB-I2C-M-Hs-Mode Controller IP Core interfaces a microprocessor via the AMBA AXI / AHB / APB Bus or Avalon Bus to an I2C Bus in Hs-Mode (3.4 Mbit/s) / Fast-Mode Plus (1 Mbit/s) / Fast-Mode (400 Kbit/s) / Standard-Mode (100 Kbit/s). The DB-I2C-M-Hs-Mode Controller IP Core can also interface a set of Registers within an ASIC / ASSP / FPGA device as well as interface Memory (e.g. SDRAM / SRAM / FLASH) to an I2C Bus.

The I2C is a two-wire bidirectional interface standard (SCL is Clock, SDA is Data) for transfer of bytes of information between two or more compliant I2C devices, typically with a microprocessor behind the master controller and one or more slave devices.

The DB-I2C-M-Hs-Mode is a Master I2C Controller that controls the Transmit or Receive of data to or from slave I2C devices. Figure 1 depicts the system view of the DB-I2C-M-AHB Controller IP Core embedded within an integrated circuit device.

In an ASIC / ASSP / FPGA integrated circuit, typically, the microprocessor is an ARM processor, but can be any embedded processor. Figure 1 depicts the system view of the DB-I2C-M-Hs-Mode Controller IP Core embedded within an integrated circuit device with its Microprocessor Configuration.

The DB-I2C-M-Hs-Mode Controller IP Core targets embedded processor applications with higher performance algorithm requirements. While most I2C controllers require high processor interaction involvement, the DB-I2C-M-Hs-Mode contains a parameterized FIFO and Finite State Machine Control for the processor to off-load the I2C transfer to the DB-I2C-M-Hs-Mode Controller. Thus, while the DB-I2C-M-Hs-Mode is busy, independently controlling the I2C Master-Transmit or Master-Receive transaction of data, the processor can complete other tasks. All Master Transmit / Receive transfers are with respect to the internal FIFO, thus fully isolating the processor from the I2C transfer of a block of data.

Key Features

Master I2C Controller Modes:
- Master – Transmitter
- Master – Receiver
Supports four I2C bus speeds:
- Hs-Mode (3.4+ Mb/s)
- Fast Mode Plus (1 Mbit/s)
- Fast Mode (400 Kb/s)
- Standard Mode (100 Kb/s)
Parameterized FIFO memory for off-loading the I2C transfers from the processor:
- Targets embedded processors with higher performance algorithm requirements, by the I2C Controller independently controlling theTransmit or Receive of bytes of information buffered to and from a FIFO.
Enhanced system-level features & integration capabilities:
- CPU Interface via parameterized FIFO with support for APB / AHB / AXI / AXI-lite / Avalon / Qsys interconnect fabrics
- Enhanced SCL / SDA spike filtering capabilities
- Enhanced Repeated Start capabilities
Enhanced system-level features & integration capabilities (Optional):
- DMA transfer between the I2C Bus & Memory (SDRAM / SRAM / FLASH)
- Direct interface to user Registers within ASIC / ASSP / FPGA device, for Master/Slave transfer across the I2C Bus
- Remote Configuration of a Digital Blocks’ I2C Slave by an I2C Master
I2C compliant features:
- Multi-Master, Clock Synchronization, Arbitration, Repeated Start, 7/10-bit addressing, & General Call Addressing, Hs-Mode
13 sources of internal interrupts with masking control
Compliance with AMBA and I2C specifications:
- Compliance with AMBA AXI / AHB/ APB Protocol Specifications
- Compliance with Avalon / Qsys Protocol Specifications
- Philips/NXP – The I2C-Bus Specification, Version 2.1, January 2000 and UM10204 Rev 7 – 1 Oct 2021
Fully-synchronous, synthesizable Verilog RTL core, with rising-edge clocking, no gated clocks, and no internal tri-states, for easy integration into FPGA or ASICdesign flows.

Block Diagram

Deliverables

The DB-I2C-M-Hs-Mode is available in synthesizable RTL Verilog or a technology specific netlist for FPGAs, along with Synopsys Design Constraints, a simulation test bench with expected results, datasheet, and user manual.

Technical Specifications

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