This IP implements a proprietary modified LZ77 algorithm and provides very high speed data compression with low latency and very high compression ratio. This IP can be used stand alone in data compression or it can be used as building block in GZIP and GLIB
High Throughput and Low Latency Data Compression Engine
Overview
Key Features
- Compression Ratio
- Delivers the best compression ratio
- 30-40% more compression compared to competition
- Throughput
- Throughput at 4 Bytes per clock
- 5.3 Gb/s (FPGA)
- 40 Gb/s (ASIC)
- Higher throughput at 8 bytes per clock, if needed
- Latency
- 4 cycles (FPGA)
- 2 cycles (ASIC
Benefits
- Most competitor's IP either provide high throughput at low compression ratio or high compression ratio at low throughput.
- This IP provides both high throughput and high compression ratio at the same time. It has very low memory requirement.
Applications
- Networking, Storage, Big data Analytics, In place Computing
Deliverables
- RTL(verilog)
- Test bench & tests
- Document
Technical Specifications
Foundry, Node
All Foundry nodes, Synthesizable soft core
Maturity
Proven in Product
Availability
now
TSMC
Pre-Silicon:
12nm
Related IPs
- High Throughput and Low Latency Compression Engine For SSD
- 2D (vector graphics) & 3D GPU IP A GPU IP combining 3D and 2D rendering features with high performance, low power consumption, and minimum CPU load
- High performance 8-bit micro-controller with 256 bytes on-chip Data RAM, three 16-bit timer/counters, and two 16-bit dptr; 0.25um UMC Logic process.
- Very Low gate Count, Hardware level, Software Data Isolation and Master level Data protection engine.
- DDR Memory Controller IP for low power and high reliability
- DDR and LPDDR 5/4/3/2 controllers for low power and high Reliability, Availability and Serviceability (RAS) targeting automotive