High Speed SPI AHB IP Core- Serial Peripheral Interface

Overview

The Arasan High-Speed SPI - AHB IP Core provides a high-speed data communication channel between the AHB and SPI buses. The SPI - AHB bridge enables an AHB host to access a serial device at high speed through the SPI interface. The controller can be used in applications such as flash memory card and digital camera.

The Arasan High Speed SPI – AHB IP Core is an RTL design in Verilog that implements an SPI – AHB controller on an ASIC, or FPGA. The Arasan High Speed SPI – AHB IP Core has been widely used in different applications by major chip vendors.

Key Features

High Speed SPI Interface

Compliant with Motorola SPI specification
Compliant with TI SPI specification
Compliant with National Mode SPI specification
Supports both SPI Master and SPI slave Operations
Supports programmable clock polarity, clock Phases.
Supports clock pre-scaling and clock bit rate

AHB Interface

Compliance with AMBA [Rev2.0] for easy integration with SOC implementations
Supports AHB bus for varying frequency range
Supports Bus mastering DMA modes.
Supports both AHB master and AHB slave modes.
Supports interrupts.
Has transmit and receive FIFOs 32x32 to accelerate the data transfers to AHB and SPI domains.

Benefits

Fully compliant core
Premier direct support from Arasan IP core designers
Easy-to-use industry standard test environment
Un-encrypted source code allows easy implementation Reuse Methodology
Manual guidelines (RMM) compliant verilog code ensured

Deliverables

Verilog HDL
Synopsis synthesis scripts
Test Environment and test scripts
SPI - AHB controller’s Userguide with full programming interface and parameterization instructions.

Technical Specifications

Maturity

Silicon proven

Availability

Now

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