High Performance NVMe for PCIe-based storage

Overview

Typical storage controllers are composed of a communication interface and a Nandflash controller. In this case, all the data flow is managed by the external host processor. However, this architecture cannot sustain high performance applications.

The IPM-NVMe_Device IP coreis a powerful data transfer manager integrated into the PCIe SSD Controller between the communication interface and the Nandflash controller, therefore off-loading the host CPU. The IPM-NVMe_Device IP is UNH-IOL NVM Express compliant. It is part of the official NVMe integrator’s list.

Server manufacturers benefit from driver standardization. All PCIe SSDs NVM Express-compliant support a unique driver providing ease-of-use and cost-reduced software development. The IP-Maker IPM-NVMe_Device IP core is fully-featured and easy to use in FPGA and SoC designs. The full hardware architecture, which is gates number optimized, provides a power efficient IOPS rate, leading to low power SSD controller capabilities.

Key Features

  • NVM Express Compliant
  • Automatic Command Processing
  • Multi-Channel DMA
  • Up to 65536 I/O queues
  • Weighted round robin queue arbitration support
  • All commands/log management
  • Legacy interrupt/MSI/MSI-X support
  • Full NVMe registers support
  • Asynchronous event management
  • Low Power architecture
  • Available for PCIe Gen1/2/3/4/5/6
  • Host Memory Buffer management
  • Controller Memory Buffer management

Benefits

  • Available for PCIe Gen1/2/3/4/5/6
  • Ultra low latency
  • Very high throughput
  • Low power architecture
  • Low gate count
  • Cost reduction thanks to interface standardization
  • Validated IP reduces time tomarket

Block Diagram

High Performance NVMe for PCIe-based storage Block Diagram

Video

This is the NVM Express demo from IP-Maker demonstrated at Flash Memory Summit 2012, Santa Clara, CA. The NVMe IP is integrated in a FPGA-based board including all the mandatory features of the NVM Express specification 1.0d. NVMe protocol is observed wit

This is the NVM Express demo from IP-Maker demonstrated at Flash Memory Summit 2012, Santa Clara, CA. The NVMe IP is integrated in a FPGA-based board including all the mandatory features of the NVM Express specification 1.0d. NVMe protocol is observed with a protocol analyzer from Teledyne Lecroy.

Deliverables

  • Verilog RTL source code
  • Low level firmware
  • Synthesis scripts
  • Technical documentation
  • Technical support

Technical Specifications

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Semiconductor IP