Memory and storage security involves protecting storage resources and the data stored on them, both on-premises and in external data centers and the cloud.
With the tremendous data and bandwidth growth in our connected world, security is essential to protect private and sensitive data as it moves across systems to storage, including memory. While the volume and variety of data are growing, so is the need for higher capacity, faster access, and accelerated processing. Designers are turning to high-performance, low-latency memory encryption solutions to preserve performance while protecting data over the latest generations of DDR, LPDDR, GDDR, and HBM memory interfaces.
AES-XTS, or as it is sometimes referred XTS-AES, is the de-facto cryptographic algorithm for protecting the confidentiality of data-at-rest on storage devices. It is a standards-based symmetric algorithm defined by NIST SP800-38E and
IEEE Std 1619-2018 specifications. It allows for pipelined architectures that can scale in performance to Terabits per second (Tbps) bandwidth.
High-Performance AES-XTS/ECB IP
Overview
Benefits
- Scalable high-performance & low latency AES-XTS/ECB cores with efficient support for varied networking traffic
- Standards compliant: NIST SP800-90-38E and IEEE Std 1619-2018
- Two customer configurable IP cores with scalable throughput, 64 bits/cycle, 128 bits/cycle (up to 128 Gbps @ 1 GHz), 256 to 4096 bits/cycle (up to 4 Tbps @ 1 GHz)
- Encrypt/Decrypt/Bypass
- Modes: AES-XTS, AES-ECB
- 128 & 256-bit AES key sizes
- NIST FIPS 140-3 security certification ready. Passed NIST CAVP validation.
- One tweak/cycle precomputation
- Latency as low as 4 cycles
- Up to 64K crypto contexts
- Message interleaving
- Secure key port
- Multi-clock domain
- Configurable CipherText Stealing (CTS) support
- Random memory block sequence access
- Optional support for OSCCA SM4-XTS
Applications
- Memory and storage security for High-Performance Computing (HPC), Data Centers, Mobile, and IoT
- DDR/LPDDR, HBM
- SSD, HDD, UFS
Deliverables
- Verilog HDL
- Testbench
- Sample synthesis script & constraints
- Sample simulation script
- Documentation
Technical Specifications
Maturity
Available on request
Availability
Available
Related IPs
- High-performance 2D (sprite graphics) GPU IP combining high pixel processing capacity and minimum gate count.
- High-performance, low-power 2D composition IP core for embedded devices
- High-performance and low-power 2D vector graphics IP core
- High-performance and low-power 3D graphics IP core
- High-Performance Single Data Rate SDRAM Controller
- Complete memory system supporting any combinations of SDR SDRAM, DDR, DDR2, Mobile SDR, FCRAM, Flash, EEPROM, SRAM and NAND Flash, all in one IP core