The HDMI IP is designed for transmitting or receiving video and audio signals between the video source devices and display devices. It is fully compliant with HDMI2.1, 2.0, 1.4 and DVI 1.0 specifications. The IP provides both PHY and controller solutions, offering a reliable implementation for HDMI interfaces that can be seamlessly integrated into the SoCs used in multimedia devices.
The HDMI Transmitter integrates four data channels, a low-jitter PLL, and a bias circuit to deliver high-quality multimedia data. The controller receives video, audio, synchronization signals, and control signals from SoC logic. These signals are merged, scrambled and encoded by the controller for transmission.
The HDMI Receiver separates the incoming data stream into audio data, video data, and packet data information. The video interface supports a variety of video formats including RGB444, YUV444, YUV422, and YUV420. The audio interface includes up to four I2S outputs, SPDIF outputs and a parallel audio output, providing comprehensive support for HDMI audio formats.
