HDMI 20 TX/RX PHY

Overview

The HDMI Rx PHY is the physical layer of an HDMI receiver. The HDMI Rx PHY implements the analog front-end (AFE) of an HDMI receiver, the sampling and deserialization of the three data streams, and the digital circuitry for TMDS decoding and operating mode management, providing a digital interface to the link controller. The HDMI Rx PHY integrates auto-calibrated input termination resistors and automatic adaptive line equalization for long cable support. An additional clock receiver is included for reference system clock reception.

Key Features

? 25–340 MHz TMDS input clock (on HDMI cable)
? Up to 1080p at 120 Hz and 4k x 2k at 60 Hz HDTV display resolutions and up to QXGA graphic display resolutions
? True-color (24-bit) and Deep-color (30, 36, or 48-bit) color resolution modes
? Up to 18 Gbps total throughput
? I 2 C interface for configuration
? JTAG interface for configuration
? Built-in Self-Test (BIST)
? Link controller flexible interface with 30-, 60-, 120-bit SDR data access
? Small core area
? Low power consumption
? Power collapsing
? Programmable terminations
? ARC TX add-on block
? 5V protection
? Embedded A/D converter and analog test bus for ATE testing
? Built-in pattern generator
? I/O continuity test

Deliverables

We offer high-speed interface IPs designed for 28~90nm fabrication processes in various foundries. We can also customize porting IPs for customers requiring 90~180nm fabrications and support more advanced processes as needed.

Technical Specifications

Foundry, Node

TSMC,40; SMIC,40

Maturity

Silicon Proven

Availability

Immediate

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HDMI 20 TX/RX PHY

Overview

Key Features

Deliverables

Technical Specifications

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