A USB 2.0 Device IP Core that provides high performance small footprint solution for quick and easy implementation of a USB Device interface.
An USB 2.0 Device IP Core is ideal for applications where the target device must act as aperipheral only. It provides portable devices with a cost-effective way of conducting point-to-point communications using the USB bus.
ARCHITECTURE
The USB 2.0 Device IP Core supports both High Speed and Full Speed operations. It will automatically perform the required negotiation to determine if it's counter part supports High Speed and fall back to Full Speed operation if it does not. The speed negotiation is supported in device and host modes.
UTMI+ L2 PHY Interface
The USB 2.0 Device IP Core features an industry standard UTMI+ L2 interface. Any of-the-shelf UTMI+ L2 compliant PHY or PHY IP can be used with this IP Core.
ULPI Interface
An optional ULPI interface is provided for interface to a ULPI compliant PHY. The ULPI interface option reduces the typical pin count of UTMI+ L2 from over 30 to just 12 interface signals.
MCU Interfaces
The USB2.0Device IP Core features two WISHBONE interfaces:
The Slave Interface is used to access all core internal registers.
The Master Interface allows the USB 2.0 Device IP Core to share the system memory for buffering data. It is also used to store Transfer Descriptors when operating in Host Mode.
Buffer Memory
The USB 2.0 Device IP Core does not need dedicated buffer memory. It's WISHONE Master Interface and the internal DMA engine allow it to share the SoC's main memory for its buffers. Optionally we can also provide a WISHBONE bridge to attach standard dedicated SRAM.
